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Jay_Jayjay
Newbie
Newbie
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Registered: ‎04-13-2021

Handshake in block diagram is separated

Hello!

When I try to use a handshaking module in a block diagram, the valid signal is on the input (left) side, the ready signal is on the output/right side. 

I can't use verilog due to the complexity (like rings in the dataflow representation) of the block diagram. 

Are there any fixes?

Thanks in advance!

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Jay_Jayjay
Newbie
Newbie
93 Views
Registered: ‎04-13-2021

Any tips? Perhaps there are specific signal names for this?

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