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Contributor
Contributor
8,644 Views
Registered: ‎12-07-2015

Hard macro Instantiation

Hi, Please explain in details how can I instantiate a hard macro.

I have create the hard macro and I place it with the rest VHDL/verilog codes.

I was trying to instantiate it as a usual componet/module and the XST (ISE 14.2/nt64) give me the below message

Line 386: Instantiating from unknown module

 

Can you help me?

Thank you.

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5 Replies
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Anonymous
Not applicable
8,619 Views

Hi,

 

Can you post the minimal code for you attempt so far that give you that error message? Pref a 50 line or so example.

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Contributor
Contributor
8,579 Views
Registered: ‎12-07-2015

Hi,

 

below is my component instantiation (hard macro)

Thank you.

 

my_design my_design(
.signal1_in(in_bits),
.signal2_in(tmp),
.signal_out(tmp_tmp)
);

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Xilinx Employee
Xilinx Employee
8,569 Views
Registered: ‎07-21-2014

Hi,
Have you included all the required files into the project?

-Shreyas
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Contributor
Contributor
8,565 Views
Registered: ‎12-07-2015

Hi,

 

I have include my_design.nmc file in the ISE (ise 14.2) project.

In addition, I was trying for a schematic my_design.sym but nothing good happens.

Thank you.

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Contributor
Contributor
8,489 Views
Registered: ‎12-07-2015

Hi,

please tell me what other file is requeried expept .nmc?

Thank you.

Regards.

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