04-09-2016 02:43 PM
Hi, Please explain in details how can I instantiate a hard macro.
I have create the hard macro and I place it with the rest VHDL/verilog codes.
I was trying to instantiate it as a usual componet/module and the XST (ISE 14.2/nt64) give me the below message
Line 386: Instantiating from unknown module
Can you help me?
04-10-2016 08:29 AM
04-10-2016 08:35 AM
I have include my_design.nmc file in the ISE (ise 14.2) project.
In addition, I was trying for a schematic my_design.sym but nothing good happens.