UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,281 Views
Registered: ‎10-20-2017

Hardware Handoff file cannot be generated as Block Diagram *.xci is not generated error

Jump to solution

Hi all,

 

I have a project that has multiple locked IP cores (for example, 'proj/Cores/pcie_7x_x4gen2/pcie_7x.xci'). These cores were generated external to the project and added as sources by pointing to the xci files.

 

The project synthesizes and completes implementation and bitstream generation. However, when I try to export the project to develop the SW application for embedded MicorBlaze, the export fails with error 'ERROR: [Vivado_Tcl 4-427] Hardware Handoff file cannot be generated as Block Diagram C:/proj/Cores/pcie_7x_x4gen2/pcie_7x.xci' is not generated.

 

A quick scan through the TCL file generated by 'write_project_tcl' shows that the core has been correctly added as a source. Also, the path pointing at the core is correct and has the xci file highlighted by the error. 

 

What would be the correct process to resolve this?

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
1,740 Views
Registered: ‎11-09-2015

Re: Hardware Handoff file cannot be generated as Block Diagram *.xci is not generated error

Jump to solution

Hi @rahul.gosavi9,

 

Try to upgrade the IPs using tools>report>report IP status.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
2 Replies
Moderator
Moderator
1,741 Views
Registered: ‎11-09-2015

Re: Hardware Handoff file cannot be generated as Block Diagram *.xci is not generated error

Jump to solution

Hi @rahul.gosavi9,

 

Try to upgrade the IPs using tools>report>report IP status.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor david.rios
Visitor
160 Views
Registered: ‎07-26-2018

Re: Hardware Handoff file cannot be generated as Block Diagram *.xci is not generated error

Jump to solution

Hi,

I have the same error when running vivado in tcl mode:

 

ERROR: [Vivado_Tcl 4-427] Hardware Handoff file cannot be generated as Block Diagram ../../../dev/test_vivado_xpr/test_vivado/Src/xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci is not generated

 

i got this error after lunching this command:

 

write_hwdef -force -file ../../dev/test_vivado/Src/xilinx/vivado/project.sdk/top.hdf

 

 

The IP is an user managed IP. when i run the report ip status, everything is up to date. for the user managed ip i got:

 

+-----------------------------------+-----------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| user_managed_IP | User-managed IP | Manage IP | *(34) | Memory Interface | 2.4 | 2.4 (Rev. 1) | Included | xc7a100tfgg484-2 |
| | | | | Generator (MIG 7 | (Rev. | | | |
| | | | | Series) | 1) | | | |

I have a script that allow to regenerate the ip. The script is run before synthesis and P&R:

 

 

# Enable MIG
set_propertyis_managed true [get_files  ../../xilinx_ip/vivado/verilog/user_managed_IP.xci]
# Switch to Verilog mode
set_property target_language Verilog [current_project]
# Generate IP
set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_PARAM {Custom}] [get_ips user_managed_IP]
generate_target {instantiation_template} [get_files ../../xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci]

# Generate Output Products
generate_target all [get_files ../../xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci]
export_ip_user_files -of_objects [get_files ../../xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci] -no_script -force -quiet
export_simulation -of_objects [get_files ../../xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci] -directory ./project.ip_user_files/sim_scripts -force -quiet

# Launch Synthesis
reset_run user_managed_IP
launch_run -jobs 6 user_managed_IP

# Switch to VHDL mode
set_property target_language VHDL [current_project]

# Disable MIG
set_property is_managed false [get_files  ../../xilinx_ip/vivado/verilog/user_managed_IP/user_managed_IP.xci]

Anyone knows a solution?

Best regards

David R.

 

0 Kudos