12-26-2016 08:01 AM
I have hold time violation in my design, the timing summary shown below.
How do i set it right.? what are the general steps? (any helpful link or material..?)
Thanks a lot in advance.
12-26-2016 08:50 AM
Try with explore with hold fix directive.
12-26-2016 09:43 AM - edited 12-26-2016 09:44 AM
You really haven't given us much information to work with. The timing violations appear to be on the same clock domain (since they are Intra-Clock paths), so that rules out the most common cause (missing constraints having to do with clock crossing).
The magnitude of the failures is very small, but the number is very large. This is unusual... Are you sure you are not looking at a post-synthesis or post-placement (as opposed to a post-implementation) timing report? Hold time fixing is mostly done by the router...
You need to show us the failing path and your timing constraints in order for us to be able to give you any more information. For example, are they "normal" flip-flop to flip-flop paths or are they associated with inputs or outputs?
12-27-2016 06:29 AM
Can you please try with Performance Explore directive?
06-20-2017 01:45 AM
A short feedback from @arpansur solution, even though I did not create this thread.
My design have met some hold timing violation (obviously, according to the STA my design is too fast).
I have tried to switch implementation strategy from "Vivado implementation default" to "Performance Explore", but it got worst. More timing violations (Setup violation and more Hold violation).
After reading the ug904, I switch back to "Vivado implementation default" and enable "phys_opt_design" in implementation setting and add "-hold_fix" in more options. All the hold violation timing has been vanished after a new implementation.