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bitjockey
Adventurer
Adventurer
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Registered: ‎03-21-2011

How To Set Different Constraint Files/Sets Between Implementations?

How can I configure a project to have different implementation constraints between two implementations of the same synthesis?

Within the project I often have different synthesis targets for different compilations (generics set differently for features, etc.) however I also have the need to target two boards with identical synthesized logic (but different PAR).

I'd like to have three constraint files in two sets:  project_timing.xdc (common), standard_pins.xdc (set 1), jerry_messed_up_the_rev00_PCB_pins.xdc (set 2).   Then have impl_1 use constr_1, and impl_2 use constr_2 set.  The timing constraint can be synth+impl and the pins can be impl-only constraints.

However when i try to do this the constraint set seems to be a property of synthesis?  I make impl_2 active, change the constraint set, but when I make impl_1 active again it has 2's constraint set; they aren't independent.  Is there any way to do this without resynthesizing? I just want to place-and-route for a different I/O pin mapping (and shame Jerry for making me version control two bitfiles, thanks Jerry).

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maps-mpls
Mentor
Mentor
204 Views
Registered: ‎06-20-2017

First, you should mark those constraints that are for synthesis as synthesis only. 

maps-mpls_4-1618010482726.png

 

The constraint file is an object the database, and you can add this property a number of ways.

Then create a second and/or third constraint set. 

maps-mpls_0-1618009967390.png

maps-mpls_2-1618010126896.png

maps-mpls_3-1618010164618.png

 

For example:

1.  Constraint set 1:  synthesis only constraints

2.  Constraint set 2:  implementation 1 constraints.

3.  Constraint set 3:  Implementation 2 constraints.

Then, in your design runs tab, create a new design run, "implementation only".  Then as you go through the wizard, select the constraint set 3 for it.  Go back to your implementation 1 and set it to use constraint set 2.

maps-mpls_1-1618010070290.png

At the end of this, select "Do not launch now"

 

maps-mpls_5-1618010531058.png

 

Then, you can launch both implementations from your runs manager by selecting your runs, and hitting the green ideograph (big tech is dumbing us down):

 

maps-mpls_6-1618010584031.png

 

I have not tried this recently, so if it doesn't work, remember how much you paid for this tip.  But this should be enough to get you on the right path, if there are any gotchas you run into.

 

*** Destination: Rapid design and development cycles ***
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bitjockey
Adventurer
Adventurer
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Registered: ‎03-21-2011

OK, so I'm not insane, it *should* work the way I thought it would work. It just didn't.

I don't have a synthesis-only xdc. I have synth AND impl constraints (mostly clock declaration and timing) and implementation only constraints (pin selection, IO standards, pullup/downs, which logical synth should care nothing about).  But I have the equivalent to your constr_2 and constr_3 sets already with xdc A and B and A and C respectively (I suppose to my example, constr_1 is an overlapping set that includes the same common xdc file A as 2 and 3 but not the unique B&C ones. Or optionally I could just pass it either set 2 or 3, and rely on the "impl only" of one of the two files in the set.)

What you describe is what I was attempting and how I assumed it should work.  However as of v2018.1 if I make impl_1 active and set, and set the constraints of this impl to constr_2, it seems to apply to the entire parent (synth) run?  Thus if I make impl_2 active and try to assign it constr_3 then that takes over for both implementations.  If I go back to impl_1 now it incorrectly is "remembering" that I had changed the project/synth to constr_3 not 2.

Is there some kind of bug where you can only add impl constraints when creating a new impl or else the GUI thinks they are for the synth run (even when containing all impl-only or dual type files) if trying to edit an existing run/impl?  Or perhaps I was doing something wrong and the gui didn't think I was trying to edit the applicable constraint fileset of the implementation and not the synthesis somehow?  I can't believe this would be a bug that Xilinx would allow to last to or beyond v2018.1.

<soap box> Also, Xilinx screwed the UX pooch here a bit.  The extra layer of indirection of "sets" along with 'when applicable" check-boxes is confusing, error prone, redundant and unnecessary.  Just let each impl/synth run specify an array/list of constraint files directly.   For instance if you end up defining a 1:1 set-to-run mapping, whats the point of the "where used" check-boxes.  Just don't include impl xdc in any set referenced by a synth run and vice versa.  </soap box>

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