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Explorer
Explorer
12,411 Views
Registered: ‎02-24-2016

How add signals from RTL to Debug Core?

Hi All,

 

I want to add signals to Debug Core. How can I do this from RTL Code (Verilog)? Actually I want to add signals, which are declared as inputs, outputs, regs and wires. What attributes should I add in the RTL code so that these signals will be added automatically to the Debug Core?

 

Thank you!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: How add signals from RTL to Debug Core?

Please refer this tutorial 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug936-vivado-tutorial-programming-debugging.pdf

Thanks and Regards
Balkrishan
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Explorer
Explorer
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Registered: ‎02-24-2016

Re: How add signals from RTL to Debug Core?

Is there a way to mark ALL the signals in the hierarchy to be inserted into a Debug Core?

 

Something like following:

(* mark_debug = "true" *) <module_name> <instance_name> (... ports ...);

 

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Moderator
Moderator
12,389 Views
Registered: ‎06-24-2015

Re: How add signals from RTL to Debug Core?

@dmitry1417

 

Better if you use the XDC Syntax:
set_property MARK_DEBUG value [get_nets <net_name>]
Where <net_name> is a signal name.
XDC Syntax Example:
set_property MARK_DEBUG TRUE [get_nets debug_wire]

 

Refer page 53-54 of this link for syntax: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug901-vivado-synthesis.pdf

Thanks,
Nupur
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Explorer
Explorer
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Registered: ‎02-24-2016

Re: How add signals from RTL to Debug Core?

When I add the (* mark_debug = "true" *) attribute to the signals in the RTL, will the debug core (*.ltx file) be created automatically?

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Moderator
Moderator
12,378 Views
Registered: ‎07-01-2015

Re: How add signals from RTL to Debug Core?

Hi @dmitry1417,

 

 

No it won't be the case. You have to insert ILA to proceed. Use the below steps:

  1. Open synthesized design
  2. Use setup debug wizard then finish the flow
  3. Save the design
  4. Run implementation. Then .ltx file will be generated.
Thanks,
Arpan
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Moderator
Moderator
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Registered: ‎07-01-2015

Re: How add signals from RTL to Debug Core?

Hi @dmitry1417,

 

Were the suggestions provided helpful?

Thanks,
Arpan
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Explorer
Explorer
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Registered: ‎02-24-2016

Re: How add signals from RTL to Debug Core?

You wrote:


 

Better if you use the XDC Syntax:
set_property MARK_DEBUG value [get_nets <net_name>]

Why this approach is batter than adding (* MARK_DEBUG = “TRUE” *) attribute into RTL?

 

As for the XDC commands, they are applied on the Netlist. But the RTL signals may be eliminated/reduced during the synthesis and will not present in the Netlist...

 

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Scholar
Scholar
12,251 Views
Registered: ‎09-16-2009

Re: How add signals from RTL to Debug Core?

@dmitry1417

 

Like you, I prefer to insert within RTL, rather than use the XDC as Nupur suggested - precisely for the reasons you state. It's far easier to find the signals your interested in within the RTL, rather than a synthesized netlist.

 

I've found, however that I need to be rather explicit, or my signals names don't always come through correctly all the way to the analyzer.  Here's what I do - I create a generic ILA, usually 255 bits wide by some depth.  Then, in my RTL, assign the debug signals I'm interested in like so:

  wire [255 : 0] debug_bus;
  (* mark_debug = "yes" *) wire            probe_m_axi_lite_bresp = m_axi_lite.bresp;
  (* mark_debug = "yes" *) wire            probe_m_axi_lite_bready = m_axi_lite.bready;
  (* mark_debug = "yes" *) wire            probe_m_axi_lite_bvalid = m_axi_lite.bvalid;
(* mark_debug = "yes" *) wire [ 31 : 0 ] probe_m_axi_lite_wdata = m_axi_lite.wdata;

// etc..

 

Then, hook up the "debug_bus" - assigning bits as needed:

  assign debug_bus[       141 ] = probe_m_axi_lite_bresp;
  assign debug_bus[       140 ] = probe_m_axi_lite_bready;
  assign debug_bus[       139 ] = probe_m_axi_lite_bvalid;
  assign debug_bus[ 138 : 107 ] = probe_m_axi_lite_wdata;

//etc.

Then, attach "debug_bus" to the ILA:

  ila_1_256_2048 ila( .clk( axi_lite_clk_i ), .probe0( debug_bus ) );

The LTX file can be created, within Vivado with the following command (sometime after synthesis):

 write_debug_probes debug_setup.ltx

With this flow, we've been able to get reliable probes, with reliable names within the analyzer.

 

As to you're question on how to add "all" signals within a module.  I don't think there's a way to do this - at least within the RTL.  Are you sure you want all? - sure that's easier.  But probing all the signals within a module is likely to fill your FPGA up VERY quickly.  You're normally going to be constrained to pick your signals with a little more precision.

 

Regards,

 

Mark

 

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Observer
Observer
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Registered: ‎04-05-2018

Re: How add signals from RTL to Debug Core?


Hi Mark,

 

thank you so much for this.

 

i do some questions though, what i do somewhat similar what is stated but i need to manually delete some signal (addr_test 4 bit enough for me from actual 16 bit or data 8 bit enough for me from 64 bit wide).

 

i have 2 questions :

 

1) will this work for the selection of bits while marking.

(* mark_debug = "true" *) wire [3:0] some_addr[3:0];

 

2) can we have this probes in multiple files in a hierarchy and it will detect the core 

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Scholar
Scholar
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Registered: ‎09-16-2009

Re: How add signals from RTL to Debug Core?


@faizan.sayed wrote:

 

i do some questions though, what i do somewhat similar what is stated but i need to manually delete some signal (addr_test 4 bit enough for me from actual 16 bit or data 8 bit enough for me from 64 bit wide).

 

i have 2 questions :

 

1) will this work for the selection of bits while marking.

(* mark_debug = "true" *) wire [3:0] some_addr[3:0];

 


I'd like to help, but I'm having trouble understanding what you're trying to do.  Is your question about using the mark_debug attribute on a two-dimensional wire?  If so, I've not tried it.  It may work, but I'd wonder what the tool would do to the signal name in the analyzer.  I'd expect some mangling of the name would occur within the LTX file (and hence the displayed name in the Analyzer)

 


@faizan.sayed wrote:

 

2) can we have this probes in multiple files in a hierarchy and it will detect the core 


For the method I posted you're specifically instantiating the ILA core.  So if you have more than once instance of your module, then yes, you'll have more than one ILA core instance as well, and the tool will do the correct thing.

 

Regards,

 

Mark

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