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Adventurer
Adventurer
1,251 Views
Registered: ‎05-18-2018

How do I change a port type in Vivado without deleting and re-adding it?

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I am fairly new to both Vivado and TCL, so I figured I would kill two birds with one stone, since I'd like to get a better handle on TCL.

Say I create a port in the block diagram and set the 'type' to 'data'.  (See attached screengrab.) If I want to later change the type to 'clk', in the Block Design editor of Vivado 2018.3 I apparently must delete the port and then re-add it to the BD, since External Port Properties panel will not allow me to change the 'type' field.

1) Can I change the 'type' field with a TCL command that simply changes that field and leaves the port name, direction, width, etc., intact?

2) Does the type field actually affect synthesis or implementation, or is it for organizational purposes?

 

Thanks.

port_type_change_1.png
port_type_change_2.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

@joelschad 

The property TYPE associated with any BD port is a read-only property.

which means once you create a port by selecting type as reset it is assigned to that port and user can not change it.

The only way around is to delete and create a new port. (as you mentioned)

 

also setting the port type affects the flow.

for example, if you set a port type as a clock then synthesis will insert BUFG's and Implementation will use clock routing resources for the net associated with that particular port.

 

and also for the purpose of organization of ports

for example, to collect all external resets of the BD you can use the following command

show_objects -name find_1 [get_bd_ports -filter { TYPE =~ "*rst*" } ]

 

The best way to not to get in this blunder is to use Make External instead of Create Port... for Xilinx IP's

--Suraj

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Xilinx Employee
Xilinx Employee
1,216 Views
Registered: ‎01-30-2019

@joelschad 

The property TYPE associated with any BD port is a read-only property.

which means once you create a port by selecting type as reset it is assigned to that port and user can not change it.

The only way around is to delete and create a new port. (as you mentioned)

 

also setting the port type affects the flow.

for example, if you set a port type as a clock then synthesis will insert BUFG's and Implementation will use clock routing resources for the net associated with that particular port.

 

and also for the purpose of organization of ports

for example, to collect all external resets of the BD you can use the following command

show_objects -name find_1 [get_bd_ports -filter { TYPE =~ "*rst*" } ]

 

The best way to not to get in this blunder is to use Make External instead of Create Port... for Xilinx IP's

--Suraj

View solution in original post

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