05-10-2019 09:12 AM
I am relatively new to Vivado and am trying to migrate a ZYNQ 7000 design over to a ZYNQ UltraScale+ design.
In the older 7000 design, which I did not create, I see a large number of IO situated along the edge of the Processing System block in the GUI.
In my UltraScale+ design, I've enabled (most of) the equivalent MIO-using blocks in my IP re-customization screen, but none of the IO show up on the Processing System block in the GUI.
How do I make these ports available in the GUI?
05-13-2019 12:39 AM
Hi @joelschad ,
With the ZynqUS+ you will only see the IOs which are effectively going to the PL. The IOs which are directly connected to the io of the chips do not appear anymore in the block design (there is no point to have them). This is why there are some you are not seeing.
05-14-2019 05:11 AM - edited 05-14-2019 05:14 AM
To add to the prior reply, Processing System functions that are routed to EMIO pins show on the Processing System block (default: zynq_ultra_ps_e_0 for ZYNQ US+, processing_system7_0 for ZYNQ 7000) in the Block Design screen. Functions routed to MIO pins do not show.