07-20-2016 06:26 AM
In my project, I am using Xilinx's Divider Generator IP core. Currently, the way I am doing this is by placing the core in a block diagram by itself, wrapping the diagram and instantiating the wrapper in a verilog module. It looks like this :
Now I want to be able to use a parameter known by my_verilog_module to be able to customize the divider's parameters (specifically the divisor width, fractional width and divident width). How would I go about doing this? Using the divider IP without using a block module is acceptable as well. I am using Vivado 2016.2
Thank you in advance,
07-20-2016 03:08 PM - edited 07-20-2016 03:11 PM
you shouldn't need the intermediate stages of bd_wrapper & bd at all. Generate the IP without BD usage and instantiate it manually directly. ie click on "ip catalog" in "project manager" window on the left and select & generate your IP; you will get a veo file which shows you how to instantiate.
07-21-2016 02:19 AM
Thank you for the reply.
I was able to use the .veo file to bypass the block diagram which was helpful. However, I am still unable to figure out how to parameratize the values for the divider. I have tried to do it like I would for a regular verilog parameter
div_gen_0#(.FRACTIONAL_WIDTH(32)) dividerUnit ( .aclk(clk), ...
And I have also tried to set a generic/parameter through the project settings and use that value while customizing the Divider
But neither worked. I noticed that in the generated (read only) file div_gen_0 the parameters were set like so :
BEGIN U0 : div_gen_v5_1_10 GENERIC MAP ( C_XDEVICEFAMILY => "artix7", C_HAS_ARESETN => 0, C_HAS_ACLKEN => 0, C_LATENCY => 26, ALGORITHM_TYPE => 3, DIVISOR_WIDTH => 24,
Is there any way to replace those constants with a parameter?
07-25-2016 02:00 AM