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rjen
Visitor
Visitor
5,836 Views
Registered: ‎11-01-2013

How to access xco parameters from vhdl

Hi there,

 

I'd like to use the LogiCORE IP Multiplier v11.2 in my design. Is there a possibility to generate the core with some generics? If yes how can I do this?

 

Otherwise the core is very unflexible to changing bitwidths. It would be nice to just regenerate the cores with new parameters and don't have to set the parameters manually in the GUI.

 

Best regards

GH

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vsrunga
Xilinx Employee
Xilinx Employee
5,826 Views
Registered: ‎07-11-2011

Hi,

 

XCO parameters can't be modified after core generation.

If  you wanted to change the bit widths of the operands then I think you can go for inference instead of core instantiation.

 

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sanhu
Contributor
Contributor
4,611 Views
Registered: ‎12-04-2014

I have the same problem.

Core generator generated fifo has fixed width and depth. I want to write a moudle which has a fifo with variable width and depth. I want to set the fifo parameter at the time I initiate the module. How can I realize it? An example module like this follows.

 

module variable_fifo #

(

    parameter data_width =8 , // default parameter, can be re-set when initiate variable_fifo

    parameter addr_width = 8 , // default parameter, can be re-set when initiate variable_fifo

    parameter fifo_depth = 256 // default parameter, can be re-set when initiate variable_fifo

)

(

    // how to initiate xilinx fifo with above parameter ?

)

endmodule

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