01-29-2014 12:22 PM
I'd like to use the LogiCORE IP Multiplier v11.2 in my design. Is there a possibility to generate the core with some generics? If yes how can I do this?
Otherwise the core is very unflexible to changing bitwidths. It would be nice to just regenerate the cores with new parameters and don't have to set the parameters manually in the GUI.
01-29-2014 04:11 PM
XCO parameters can't be modified after core generation.
If you wanted to change the bit widths of the operands then I think you can go for inference instead of core instantiation.
12-31-2014 12:24 AM
I have the same problem.
Core generator generated fifo has fixed width and depth. I want to write a moudle which has a fifo with variable width and depth. I want to set the fifo parameter at the time I initiate the module. How can I realize it? An example module like this follows.
module variable_fifo #
parameter data_width =8 , // default parameter, can be re-set when initiate variable_fifo
parameter addr_width = 8 , // default parameter, can be re-set when initiate variable_fifo
parameter fifo_depth = 256 // default parameter, can be re-set when initiate variable_fifo
// how to initiate xilinx fifo with above parameter ?