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knugent
Adventurer
Adventurer
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Registered: ‎05-31-2019

How to best synthesize user generated IPs that will be used (connected up) later on at top_level top_level diagram (that includes a top_level wrapper)

Hi,

I try generating user IPs from RTL for a specific project.

What is the best synthesis approach to follow ? OOC or Global ?

Seen the IP Basics chapter 2 document that includes a diagram at page 45 differentiating the 2 flows.

Is it best to synthesize standalone ooc each IP separately ? If yes, what ooc constraints are best to use?

I am only using 1 main clock which is synchonous + using asynchronous input reset (synchonized using 2 flops) when it gets connected to the various IPs.

create_clock

set_clock_uncertainty

set_false_path

set_input_delay

set_outout_delay

set_system_jitter

set_clock_latency

 

If the IP input/output ports are not connected to the top-level what is best way to constrain them?

Do I have to create eg a virtual clock same as the main clock for this as shown below :

 

#Create the base clock for the clock port
create_clock -name {aclk} -period 5.00 -waveform {0.00 2.5} [get_ports aclk]

#Create a virtual clock with the same properties of the base clock, clock driving the source register
create_clock -name virt_aclk -period 5.00 -waveform {0.00 2.5}

set_false_path -from [get_ports aresetn]

#Apply input delay of 70% to all input ports
set_input_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports s_axis_input_tdata]
set_input_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports s_axis_input_tvalid]
set_input_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports m_axis_output_tready]

#Apply output delay of 70% to all output ports
set_output_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports m_axis_output_ser_start]
set_output_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports m_axis_output_tdata]
set_output_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports m_axis_output_tvalid]
set_output_delay -max 3.5 -clock [get_clocks {virt_aclk}] [get_ports s_axis_input_tready]

 

The main clock I am using is 200MHz (5ns). Is the input/output delays 3.5 (ie 70% of 5) realistic values to use here? Please comment.

 

I also noticed context commands and properties that have to be used eg HD.CLK_SRC, HD.PARTPIN_LOCS, HD.PARTPIN_RANGE, set_logic_unconnected, set_logic_one, set_logic_zero constraints for ooc

eg the Dual port RAM blk_mem_gen_0_ooc.xdc from IP catalog inculded the following :

create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]

What type of clock buffer is best to specify (that wil not have a big delay) and will not cause any issues with timing issues ?

eg the OBUF that the tool tried to insert at the output ports had a delay of 2.434ns  and I am using a 5ns clock period. This is almost half of the clock period and if a 3.5ns external delay is used this causes an intra-clock path - aclk setup violation from aclk source with an IBUF (0.736nS delay) all away to the registered output port that includes an OBUF (2.434nS delay)

The path described above looks like this :

input aclk -> net delay -> IBUF delay -> net delay -> FDRE flop (clk-to-q delay) -> net delay -> OBUF delay -> net delay -> output port

 

----

or is it best to use global synthesis for all IPs & top level ? 

 

My choice will be to use ooc synthesis when genertating IPs standalone but need to now all realistic constraints to use for a clock of 5ns

and how to propagate these constraints to the to top level later after synthesizing at top_level (bottom-up approach ?)

What realistic constraints should I also use at the top level? Same as the ooc but without using a virtual clock for the input/output delays?

 

Your prompt reply to this matter will be appreciated.

 

Regards,

Kevin

 

 

 

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drjohnsmith
Teacher
Teacher
432 Views
Registered: ‎07-09-2009

OOC

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