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chris_ee
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Registered: ‎07-15-2019

How to break signals out of an interface port? How to combine signals into an interface port?

Is there a way to break up an interface port into individual signals?
And then combine the individual signals into an interface port?

I am doing something similar to this question, but I'm using a SPI bus instead of AXI.  There is no corresponding "subset converter" block for SPI interface ports.

https://forums.xilinx.com/t5/Design-Entry/How-to-assemble-an-interface-port/m-p/689945

Here's the image from the original post:

chris_ee_0-1623967888793.jpeg

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chris_ee
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Registered: ‎07-15-2019

The only way I have found to do this is to create an IP block with the full SPI bus as an input and output.  The signal is broken out within the IP block. 

Templates for the bused signals in interface ports can be found in Vivado under Tools -> Language Templates, then select Verilog or VHDL-> IP Integrator HDL -> Advanced Interfaces

I'm still looking for how to do this within block designer. 

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mvisser
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Registered: ‎11-06-2018

What happens if you create a port in bd manually and then try and route the individual signal to that port directly? Basically similar to the picture you posted but without the fit timer in between the line and the port?

chris_ee
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Registered: ‎07-15-2019

I couldn't get this to work because the interface definition doesn't account for the bus as an input.  SS is defined as an output for both master and slave devices.

I ended up just creating ports for the individual SPI signals and connecting each signal as wires instead of using the bus.

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mvisser
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Registered: ‎11-06-2018

Are you ignoring the SS lines? Or how are you handling that? In my experience, mixing up input and output signals results in the lines being tied to GND in synthesis.

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