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Participant
Participant
7,279 Views
Registered: ‎10-05-2015

How to change the TDATA width during packaging IP

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Hi,

   I am trying to package a new IP. However, when I use the "create and package IP" tool in Vivado, I find that the Tdata width of AXI stream interface is fixed as 32 (i.e., no other choices). The IP to be packaged has 256-bit data width. Is there any solution to this problem? Thanks much.

 

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Participant
Participant
14,108 Views
Registered: ‎10-05-2015

I found a place to change the width in Package IP. Thanks much for your help.

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Can you post a screenshot of what you're seeing along with the HDL declaration of tdata?

Is your port width dependent on a parameter/generic?
www.xilinx.com
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Participant
Participant
14,109 Views
Registered: ‎10-05-2015

I found a place to change the width in Package IP. Thanks much for your help.

View solution in original post

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