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carnby
Explorer
Explorer
8,344 Views
Registered: ‎11-23-2013

How to change timing constraints in OOC.xdc files??

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After synthesized, I got the warning below.

[Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ddc_inst/fir_filter1_inst' at clock pin 'aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.

 

The OOC.xdc file is read only in Vivado, so I try to change the 10.000 to 5.000 in other text editor. But I find that I cannot re-synthesize the IP using new .xdc file in any way.

Because I'm using Vivado 2016.3 which does not provide the "Launch Runs..." command in "Design Runs" bar like Vivado 2015.4.

 

In Vivado 2015.4, I first change the .xdc file in text editor, and then click "Reset Runs" command to reset the IP's "Runs" result, and then click "Launch Runs..." command to run the OOC IP again. By doing this, the IP was synthesized by the new .xdc constrain.

But in Vivado 2016.3, the related command above are removed.

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vemulad
Xilinx Employee
Xilinx Employee
13,507 Views
Registered: ‎09-20-2012

Hi @carnby

 

Try the method described in page-30,31 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug896-vivado-ip.pdf

Thanks,
Deepika.
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arpansur
Moderator
Moderator
8,340 Views
Registered: ‎07-01-2015

Hi @carnby,

 

Are you using OOC per IP or global?

Thanks,
Arpan
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carnby
Explorer
Explorer
8,329 Views
Registered: ‎11-23-2013

Thanks!

I am using OOC per IP.

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arpansur
Moderator
Moderator
8,327 Views
Registered: ‎07-01-2015

Hi @carnby,

 

Then you should be able to generate the output products.

Use cached scope of IP to local and then synthesize the design.

Thanks,
Arpan
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carnby
Explorer
Explorer
8,320 Views
Registered: ‎11-23-2013

How to use cached scope of IP to local?

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arpansur
Moderator
Moderator
8,316 Views
Registered: ‎07-01-2015

Hi @carnby,

 

Go to project settings->IP

Thanks,
Arpan
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carnby
Explorer
Explorer
8,304 Views
Registered: ‎11-23-2013

Hi, arpansur!

 

I checked my settings. Cache scope was set to "local" already.

I change the clock period of the IP from 10 to 4 in "fifo_ddc_ooc.xdc" using text editor outside Vivado and then synthesized the design. The same warning still exists.

 

In version 2015.4, I can reset the runs of the OOC IP, and then launch the OOC runs in GUI. But I cannot do the same thing in 2016.3.

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vemulad
Xilinx Employee
Xilinx Employee
13,508 Views
Registered: ‎09-20-2012

Hi @carnby

 

Try the method described in page-30,31 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug896-vivado-ip.pdf

Thanks,
Deepika.
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View solution in original post

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carnby
Explorer
Explorer
8,267 Views
Registered: ‎11-23-2013

Thanks a lot! This do works.

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lyuanjie
Observer
Observer
6,831 Views
Registered: ‎10-26-2010

Hi @vemulad

 

How do you it the same for Block RAM using native interface? What properties do you change? Thanks

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sandyhelton
Visitor
Visitor
2,520 Views
Registered: ‎01-15-2018

Hi,

I have the same problem and have gone through and set the properties as per UG896. However, this did not work on FIFO's that have a read and write clock. It seems to work for the core_clk, when that is the only clock. I was able to work around the issue, by editing the ooc.xdc file with the correct periods, deleting just the dcp file and regenerating the output products. When I do this, the ooc.xdc file is not overwritten, which preserves the edits that I made. Has this issue been identified and fixed? I am currently using Vivado 2016.4.

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