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Explorer
Explorer
112 Views
Registered: ‎01-15-2019

How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

Hi All,

How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

I have two projects, which seems to be same, but behave different on the board. I want to compare between them. How can I do so?

Thank you!

 

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2 Replies
Xilinx Employee
Xilinx Employee
51 Views
Registered: ‎01-30-2019

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

hi @ldm.eth 

please see the following AR 

https://www.xilinx.com/support/answers/61599.html

and then compare the Vivado.log file of both projects, and try to find out - from which step the check sum's start differentiating?

if checksum if different during synthesis itself, then you need to check the source files of the project to find the difference?

if not then try to see if you are using the same strategy's, same tcl.pre and tcl.post, same maxthreads,  in both the projects.

 

regards

Suraj 

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Xilinx Employee
Xilinx Employee
48 Views
Registered: ‎06-27-2018

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

Hi @ldm.eth .

You should also compare the behavioral simulation and post-implementation functional simulation of the design, this will give you some idea about the changing signals and also at which step they ae changing.

~Chinmay

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