cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
534 Views
Registered: ‎01-15-2019

How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

Hi All,

How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

I have two projects, which seems to be same, but behave different on the board. I want to compare between them. How can I do so?

Thank you!

 

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
473 Views
Registered: ‎01-30-2019

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

hi @ldm.eth 

please see the following AR 

https://www.xilinx.com/support/answers/61599.html

and then compare the Vivado.log file of both projects, and try to find out - from which step the check sum's start differentiating?

if checksum if different during synthesis itself, then you need to check the source files of the project to find the difference?

if not then try to see if you are using the same strategy's, same tcl.pre and tcl.post, same maxthreads,  in both the projects.

 

regards

Suraj 

Tags (1)
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎06-27-2018

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

Hi @ldm.eth .

You should also compare the behavioral simulation and post-implementation functional simulation of the design, this will give you some idea about the changing signals and also at which step they ae changing.

~Chinmay

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
334 Views
Registered: ‎01-30-2019

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

Hi @ldm.eth ,

You can try using any netlist comparing tools like Onespin

0 Kudos
Highlighted
Teacher
Teacher
325 Views
Registered: ‎07-09-2009

Re: How to compare two projects (RTL, Block Design, Constraints, etc) in Vivado 2018?

You have two topics here

   is the design "complete" and comparison 

comparison first.

 

You have two types of comparisons, 

the first assumes that both projects are basicaly the same, and some small changes have been made , 

     if you have a text based project, then its down to a file comparison difference  tool, 

     I use windiff for thsi sort of comparison

https://en.wikipedia.org/wiki/WinDiff

 

 

The other sort of comparison is formal comparison,

     that is the holey grail of comparisons, 

you put the two units in a test bench, and apply the same simulant to the two and see what the difference of the output is

     Its actuay very hard for all but the simplest projects to be 100 % certain you have two identical units or not.

 

 

IMHO design complete is the most likely difference though , 

   many times we see people in the forums having a desing that works, they do a small change and it fails.       

         the answer most of the time, is they have missing , incomplete or incorrect constraints, 

          and its just by luck that the working desing works,  

The other thing we find is people think the tools are clever. They arn't and part of enginering IMHO is learning waht styles work in each tool 

 

If you want to post as two attatchments the two projects and your test bench Im certain some one will be able to help

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos