01-31-2019 08:50 PM
We are trying to compile ABEL code roject in Xilinx ISE 10.1 service pack 3. However, we are not able to see Synthesis tool as ABEL in ISE 10.1.We have ABEL and UCF file and we are using CPLD device.
Can you help us to compile the ABEL code?
01-31-2019 10:19 PM
Are you able to add ABEL file in your project? (As shown below, click on "open" icon and select options for ABEL and UCF)
01-31-2019 10:23 PM
Hi I am able to add ABEL and UCF file. Not able to synthesis in the tool ISE 10.1
01-31-2019 10:38 PM
What error are you facing? provide snapshot.
Also provide ABEL file to check it at my end.
02-01-2019 12:47 AM
Pease refer picture herewith. Cant provide ABEL code. Just want to know procedure for compilation for ISE 10.1
02-01-2019 04:35 AM
ISE tool does not directly synthesize abel file. First it must be converted into VHDL or Verilog file which can be done using the command called ‘XPort’.
Have a look into this AR.https://www.xilinx.com/support/answers/17000.html
02-04-2019 10:20 PM
Let us know if you have further queries on it, or close this thread by marking it as accepted solution.
02-06-2019 12:27 AM
We are getting errors in converting ABEL to VHDL. Please find attached pitcures for details.
02-06-2019 12:37 AM