11-04-2013 07:56 AM
how can I connect a 32bit AXI control stream coming from a DMA engine to a 24bit configuration stream interface of a FFT core?
Is it somehow possible to access the indivitual signals of a interface vector in the block design?
11-05-2013 12:53 AM
11-04-2013 08:06 AM
Any reason that you can't use AXI -FFT which is AXI stream compilant ?
11-04-2013 02:18 PM
The core that i am using already has axi stream ports for data in, data out and config in.
The config in port is 3 bytes wide but the control port of the DMA is 4 bytes wide. When I simply connect those graphically in the block design the design rule check fails complaining that the width doesn't match. How can I connect the 3 LSB of the DMA to the 3 bytes of the fft?
11-04-2013 02:57 PM
11-05-2013 12:31 AM
I had a look at the concat block and apparently it is doing exaclty the opposite of what I want to achieve.
I want to connect a 32bit signal to a 24 bit signal by neglecting the MSByte of the 32bit signal. Concat
allows to concatenate multiple bits or vectors to a single wider vector. In PlanAhead I just declared the ports
external and connected them in the top HDL but when I do that in Vivado I get the following error from the DRC:
[BD 41-968] AXI interface port /M_AXIS_CNTRL is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port.
I also tried to use an AXIS_subset_converter block with the slave TDATA width (bytes) set to 4 and the Master TDATA width (bytes) set to 3.
The TDATA Remap String is set to tdata[23:0].
When I try to generate the output products I get the following errors:
[Ipptcl 7-5] XIT evaluation error: File writer encountered an error: c:/Users/x/Desktop/ZED_board_projects/Vivado/fft_project/fft_project.srcs/sources_1/bd/zedboard/ip/zedboard_axis_subset_converter_0_0_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_axis_subset_converter_zedboard_axis_subset_converter_0_0.v [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2013.3/data/ip/xilinx/axis_subset_converter_v1_1/ttcl/axis_subset_converter_v1_1_axis_subset_converter_v.xit': ERROR: [Common 17-39] 'xit::puts_ipfile' failed due to earlier errors. [IP_Flow 19-911] XIT detected an open writer channel for file 'c:/Users/x/Desktop/ZED_board_projects/Vivado/fft_project/fft_project.srcs/sources_1/bd/zedboard/ip/zedboard_axis_subset_converter_0_0_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_axis_subset_converter_zedboard_axis_subset_converter_0_0.v'. Please use 'close_ipfile' command to close channels before exit. [IP_Flow 19-167] Failed to deliver one or more file(s). [IP_Flow 19-1710] Problem delivering 'Verilog Synthesis' files for IP 'zedboard_axis_subset_converter_0_0'. [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate 'Verilog Synthesis' output product for IP 'zedboard_axis_subset_converter_0_0': [BD 41-1030] Generation failed for the IP Integrator block /axis_subset_converter_0
Is it really so hard to connect these two interfaces together in Vivado or am I missing something?
Your help is appreciated!
11-05-2013 12:53 AM
11-05-2013 04:47 AM
Thank you Muzaffer,
11-28-2014 02:17 AM
I'm really interested to understand the solution. I don't understand about the 'slice'. What I found from my TDATA Remap String's axis_subset_converter is 8'b00000000,tdata[23:16],tdata[7:0],tdata[15:8]. How to make them into slices as suggested by you?
Thanks a lot for your help. Really appreaciate it.
11-28-2014 07:48 AM
8'b00000000,tdata[23:16],tdata[7:0],tdata[15:8] can be implemented as following. xslice_0 is also shown.
11-30-2014 08:30 PM
Thanks for your reply, I've tried that but still get the errors as shown below, could you please help? I attach the modified bd and its print screen for your reference. Thanks a lot!
ERROR: [IP_Flow 19-911] XIT detected an open writer channel for file 'd:/Zedboard/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2014.1.srcs/sources_1/bd/design_1/ip/design_1_axis_subset_converter_1_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_axis_subset_converter_design_1_axis_subset_converter_1_0.v'. Please use 'close_ipfile' command to close channels before exit.
11-30-2014 09:22 PM
this is a completely independent error. I think your problem is that your path is too long. Move your project to someplace higher in the folder hierarchy and make your project name shorter.
12-01-2014 02:05 AM
Thanks a lot! Your advice is really helpful! Now, I've got an error while generating the bitstream as shown below. Thanks in advance for your advice.
ERROR: [Common 17-69] Command failed: This design contains a core for which bitstream generation is not supported: design_1_i/v_cresample_1 (v_cresample Version 4)
12-01-2014 02:08 AM
Please donot post different queries on same thread.
I have created a new thread for your problem, please check this link http://forums.xilinx.com/t5/Installation-and-Licensing/Re-How-to-conect-AXI-stream-interfaces-with-different-width-in/m-p/550121 and you can follow-up there.