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araxnid
Visitor
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Registered: ‎01-28-2012

How to connect LVDS output and LVDS input inside design

Basically, all question is in subject.

 

What I have is two LVDS IP blocks - one of them is for my data output and second is for my data input. For debug purposes I want to connect them inside my design, so I can check everything works nice, but I cant get pass implementation step, because of several warnings:

 [Place 30-378] Input pin of input buffer LVDS_demodulator_input/inst/pins[0].ibufds_inst has an illegal connection to a logic constant value.

 And so on...

 

As I understand I need to add buffer between LVDS output and input, but after that it sending me a error that there is already buffers at output stage... soo, what Im doing wrong?

 

Here is code for my current implementation:

selectio_wiz_0 LVDS_modulator_output (
.data_out_to_pins_p(LVDS_mod_output_p),     // output wire [7 : 0] data_out_to_pins_p
.data_out_to_pins_n(LVDS_mod_output_n),     // output wire [7 : 0] data_out_to_pins_n
.clk_in(CLK_out_200),                       // input wire clk_in
.clock_enable(CLK_locked),                  // input wire clock_enable
.data_out_from_device(modulatorSamples),    // input wire [15 : 0] data_out_from_device
.clk_reset(RST_CLK),                        // input wire clk_reset
.io_reset(RST_DATA),                        // input wire io_reset
.clk_to_pins_p(LVDS_mod_CLK_p),             // output wire clk_to_pins_p
.clk_to_pins_n(LVDS_mod_CLK_n)              // output wire clk_to_pins_n
);

selectio_wiz_1 LVDS_demodulator_input (
.data_in_from_pins_p(LVDS_mod_output_p), // input wire [7 : 0] data_in_from_pins_p
.data_in_from_pins_n(LVDS_mod_output_n), // input wire [7 : 0] data_in_from_pins_n
.clk_in_p(LVDS_mod_CLK_p),               // input wire clk_in_p
.clk_in_n(LVDS_mod_CLK_n),               // input wire clk_in_n
.clock_enable(CLK_locked),               // input wire clock_enable
.io_reset(RST_DATA),                     // input wire io_reset
.clk_out(),                              // output wire clk_out
.data_in_to_device(demodulatorSamples)   // output wire [15 : 0] data_in_to_device
);

And here is what I tried with buffers:

selectio_wiz_1 LVDS_demodulator_input (
.data_in_from_pins_p(LVDS_buff_mod_output_p), // input wire [7 : 0] data_in_from_pins_p
.data_in_from_pins_n(LVDS_buff_mod_output_n), // input wire [7 : 0] data_in_from_pins_n
.clk_in_p(LVDS_mod_CLK_p),                    // input wire clk_in_p
.clk_in_n(LVDS_mod_CLK_n),                    // input wire clk_in_n
.clock_enable(CLK_locked),                    // input wire clock_enable
.io_reset(RST_DATA),                          // input wire io_reset
.clk_out(),                                   // output wire clk_out
.data_in_to_device(demodulatorSamples)        // output wire [15 : 0] data_in_to_device
);

IBUFDS_DIFF_OUT #(
.DIFF_TERM("FALSE"),                // Differential Termination, "TRUE"/"FALSE" 
.IBUF_LOW_PWR("FALSE"),             // Low power="TRUE", Highest performance="FALSE" 
.IOSTANDARD("LVDS")                 // Specify the input I/O standard
) IBUFDS_DIFF_OUT_lvds_dem_data[7:0] (
.O(LVDS_buff_mod_output_p[7:0]),    // Buffer diff_p output
.OB(LVDS_buff_mod_output_n[7:0]),   // Buffer diff_n output
.I(LVDS_mod_output_p[7:0]),         // Diff_p buffer input (connect directly to top-level port)
.IB(LVDS_mod_output_n[7:0])         // Diff_n buffer input (connect directly to top-level port)
);

And the error: [Drc 23-20] Rule violation (REQP-1583) IO buffers connected in series - IO buffer LVDS_demodulator_input/inst/pins[0].ibufds_inst (IBUFDS) pin LVDS_demodulator_input/inst/pins[0].ibufds_inst/I drives or is driven by another IO buffer IBUFDS_DIFF_OUT_lvds_dem_data[0]/IBUFDS (in IBUFDS_DIFF_OUT_lvds_dem_data[0] macro) (IBUFDS). To resolve this unsupported case, remove the redundant IO buffers in top-level synthesis for all ports which have embedded IO buffers in the module. If using Vivado Synthesis, set the IO_BUFFER_TYPE property to a value of 'NONE'.

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5 Replies
umamahe
Xilinx Employee
Xilinx Employee
9,316 Views
Registered: ‎08-01-2012

I believe it is not possible to connect LVDS output and LVDS input inside design. You can connect before IO (LVDS) driver i.e. at buffer stage.

 

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araxnid
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Registered: ‎01-28-2012

Sad to hear it, umamahe.

But why this is not working? I mean, they are not physical LVDS inside design, they are still usuall 'wire' type. 

I know that I can connect data before LVDS blocks, but its doesnt solve problem with debuging design :( 

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

> I mean, they are not physical LVDS inside design, they are still usuall 'wire' type.

 

An OBUFDS and IBUFDS are physical blocks with limited connectivity with O/OB and I/IB pins allowed to connect only to the top level pads.   I am unsure if there is a DRC that prevents an always on OBUFDS from being used with an IBUFDS and your original post does not indicate if an error message was generated for this.

 

The error message that you did post was for the second code snippet that has an IBUFDS_DIFF_OUT before the input of IBUFDS and this is absolutely not allowed.

 

You did not post an error message for the first code snippet, but I do notice that you are not using the same name for the output differential ports and the input differential ports.  This will form two different output ports and the tools will prevent you from assigning these to the same location.

------Have you tried typing your question into Google? If not you should before posting.
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muzaffer
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Registered: ‎03-31-2012

why doesn't connecting before & after the lvd blocks help you debug the problem? lvds tx/rx are just a way of carrying a signal in analog domain. in digital domain connecting the input to the lvds transmitter to the output of the lvds receiver should create a circuit which is identical to the one with the two buffer instantiated. bypassing lvds should allow you to debug the logic fully.
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huzaifasajids
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Registered: ‎12-09-2018

I am trying the same thing(LVDS internal loopback) but with 2 SelectIO IPs. I too am getting the error at the implementation stage. The error states as follows:

 

[Opt 31-1] OBUFDS design_1_i/selectio_wiz_0/inst/pins[0].obufds_inst O pin is not connected to a top-level port.

 

Reading the thread I think I'm sure there isn't any way for me to test this. But since the thread is pretty old, I'm hoping a solution might have emerged. If any of you has been able to resolve this, please help. Thanks.

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