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Visitor ragooman
Registered: ‎09-05-2011

How to create a Hierarchical design using a schematic

I'm trying to re-learn how to create a hierarchical design using the schematic. It's been a long time since I used ISE - about 10yrs. So things are still rusty. I'm using Verilog to program this Dev.bd, a Spartan-3 Starter Board.


From what I've been reading between the different tutorials, pdf, and webpages, it seems that the ISE method is to design with a Bottom-Up approach only, is this correct ?


I had thought it was also possible to use a Top-Down approach. Where I would define the complete circuit - all the in's and out's -  that reside on my circuit card. Then as I define the internal parts of the system and interfaces, I would add each module underneath the top level as I go along.


But when I start creating the top level and adding the various ports, and connecting the wires, the wires only connect to the I/O ports and don't seem to connect to the block. I have a visual indication of a red square over the terminating end of the wire where it supposed to connect to the block. The end which connects to the I/O port is definitely connected.


As such, the 'push down' tool button is disabled on the ISE and I can't enter the next level to create the modules.


Is their still a way to build a design using a Top-Down approach ?





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2 Replies
Teacher rcingham
Registered: ‎09-09-2010

Re: How to create a Hierarchical design using a schematic

"Is there still a way to build a design using a Top-Down approach?"

Yes - do it all in HDL...

"If it don't work in simulation, it won't work on the board."
Xilinx Employee
Xilinx Employee
Registered: ‎07-22-2008

Re: How to create a Hierarchical design using a schematic

Top-down or bottom-up methods are both supported.

In order to push into a schematic symbol, the underlying module must have been added to the Project Navigator project.  If the module does not exist yet right click on an instsance of the symbol on a schematic page and select Symbol -> Push into symbol.  A dialog box will appear stating that ISE cannot determine the module that defines the symbol.  You will be givent the option to generate a template in SCH, VHDL or VERILOG.


See: http://www.xilinx.com/support/answers/16192.htm

Note: This Answer Record is a little dated in that ABEL HDL is no longer supported but, the rest of the AR appears to be correct.

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