03-21-2020 12:23 PM
Hello, I would like to create a state machine as a separate module. The outputs will be the state.
The states are defined by a syntax similar to type states is (s1, s2, s3, s4, s5, s6 ,s7, s8);
Now, how do I create the module's ports? How can I assign the state type to it?
thanks in advance!
03-21-2020 12:43 PM
Vivado has a built-in "cheatsheet", look for a bulb icon called "language templates" when a vhdl/verilog file is open. There is a template for state machine.
Typically, FSM state variables are an enumerated variable coded to a bit vector. In your case, 8 states fit into a 3-bit vector, and that's your module output.
03-21-2020 10:35 PM