cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
318 Views
Registered: ‎03-18-2020

How to create a State machine as a separate module in VHDL?

 

Hello, I would like to create a state machine as a separate module. The outputs will be the state.

The states are defined by a syntax similar to type states is (s1, s2, s3, s4, s5, s6 ,s7, s8);

Now, how do I create the module's ports? How can I assign the state type to it?

thanks in advance!

0 Kudos
2 Replies
Highlighted
Explorer
Explorer
309 Views
Registered: ‎11-19-2010

Vivado has a built-in "cheatsheet", look for a bulb icon called "language templates" when a vhdl/verilog file is open. There is a template for state machine.

Typically, FSM state variables are an enumerated variable coded to a bit vector. In your case, 8 states fit into a 3-bit vector, and that's your module output. 

0 Kudos
Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎05-22-2018