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Anonymous
Not applicable
7,071 Views

How to create an AXI4 Master from a Verilog code automatically?

Hi, 

 

I am new to the Verilog/AXI world and I am wondering if it does exist a tool in Vivado that allow you to automatically generate an IP Core, given a Verilog code, wrapping AXI4-Master interfaces too.

 

Thanks

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

@Anonymous there is no automatic wrapping your existing verilog block. What you can do is to create a template master and then manually insert your existing code into that setup. 

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Anonymous
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@muzaffer This means that i will have to manually define each signal and define the its behaviour as specified in the AXI paradigm?

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

@Anonymous actually now that I think about it, do you actually mean that you want to make an axi-master IP or axi-slave IP ? Most probably you want the latter. Assuming that's the case, it is much easier to get Vivado to create a basic axi-slave code (lite or full) and then add your own logic to it. This way almost all protocol management, and top level connectivity of the axi is supplied by Xilinx and you only add your custom logic to it.

If you actually want a master, it is more complicated as masters are supposed to know the behavior of the slaves to which they talk. 

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baf2099
Adventurer
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Registered: ‎03-17-2017

In Vivado, if you click on the Tools menu there is an option to "Create and Package new IP". This will start a wizard that will allow you to create an AXI interface of your choosing and will generate the supporting code necessary to use it. It will open up in a new project but you can take this generated code and edit it to your liking in order to fit your application. Alternatively, you can work within the IP packager environment and build around that and actually create your own custom IP core to be utilized in other projects. Really depends on what your end game is, but if you are doing this for a Zynq based project then using IP packager will help you get your code into a block diagram with the Zynq part and make AXI connections very easy.

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