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mamisadegh3
Explorer
Explorer
11,931 Views
Registered: ‎09-19-2010

How to define a new parameter in my "Block Design" in Vivado?

Hi, 

I am pretty sure the answer to my question is some where in the documentation, but I couldn't find it. 

 

Suppose you are doing a block design in Vivado and then you want to use your designas a (packaged) sub-module in a bigger design. 

 

Now for example I want the width of my ports in this block design to be a parameter value. 

 

How do you define a new parameter inside the block design of vivado? 

 

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6 Replies
sampatd
Scholar
Scholar
11,925 Views
Registered: ‎09-05-2011

You should be able to do this using "IP customization parameters".

Follow the steps on page 62 of
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf
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mamisadegh3
Explorer
Explorer
11,906 Views
Registered: ‎09-19-2010

Hello, 

May be I don't understand the document correctly, 

 

Just, suppose that you have a block design, 

And inside your block design you have created an AXI Interface port. 

 

Now, you click on the interface port, the aximm dialog box opens, 

Now, I want to instead of entering numbers here, enter a parameter. 

 

But, as soon as I begin typing any kind of text there, it gets red and an error message is generated. 

Shouldn't we be able to define these key interface parameters as parameteric values of the design instead of fixed values?

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bokkaab
Xilinx Employee
Xilinx Employee
11,825 Views
Registered: ‎02-26-2014

while packaging a design as an IP, incase the design has generic parameters in the code , the vivado tool will automatically infer them as customization parameters and will display them under "Customization Parameters " (on double clicking the IP, the IPI window opens, "customization parameters" is displyed in it).
You could as well push the parameters,say data width of input and output ports ..etc., to a top level wrapper file from where you could customize them.
j.feldmann
Newbie
Newbie
10,856 Views
Registered: ‎06-14-2014

Hi everyone,

 

I got the same problem:

I want to package a block design as IP with some parameters used from other IPs inside my design.

How can I simply pass some parameters through my design to make them editable in the design IP package without adding generic blocks (I'm using VHDL) into the wrapper?

 

Thanks for any suggestions!

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muravin
Scholar
Scholar
10,835 Views
Registered: ‎11-21-2013

You are now stumbling on some basic scriptology. One way to try this would be creating a TCL script that contains your global parameters into a namespace. See example below.

 

namespace eval global_vars {

variable global_param1 0

variable global_param2 blockram

#  and so on...

variable global_param25 256

}

 

Then, in your /xgui folder that contains the pcore-specific tcl file, you can add a formulae something like:

 

set localparam0 [expr {$global_vars::global_param1 + $global_vars::global_param25}]

 

You can also get the same thing through GUI in the IP Packager when you mark the parameter to be updated as expression with $ etc

 

Hope this helps.

 

BR

Vlad

Vladislav Muravin
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sanhu
Contributor
Contributor
9,633 Views
Registered: ‎12-04-2014

I have the same problem.

Core generator generated fifo has fixed width and depth. I want to write a moudle which has a fifo with variable width and depth. I want to set the fifo parameter at the time I initiate the module. How can I realize it? An example module like this follows.

 

module variable_fifo #

(

    parameter data_width =8 , // default parameter, can be re-set when initiate variable_fifo

    parameter addr_width = 8 , // default parameter, can be re-set when initiate variable_fifo

    parameter fifo_depth = 256 // default parameter, can be re-set when initiate variable_fifo

)

(

    // how to initiate xilinx fifo with above parameter ?

)

endmodule

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