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Visitor venky699
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8,833 Views
Registered: ‎06-28-2013

How to enable the flop option in the ISE design Tool

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Hi,

 

  Currently I am using V6 FPGA. I heard that there is a option in the ISE tool, it will automatically do, if there is any clock gating issues means the data path and clock path dependency is there, make it as a independent paths by setting the option in the tool like "Enable the flops" or some another option like that..... If any one knows about that option, please let me know,where  we can find that option in tool and what are the things we need to take care about it?

 

 

Regards,

Venkatesh.

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Xilinx Employee
Xilinx Employee
13,200 Views
Registered: ‎09-20-2012

Re: How to enable the flop option in the ISE design Tool

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I guess you need to post this on synplify forums for more details.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,832 Views
Registered: ‎09-20-2012

Re: How to enable the flop option in the ISE design Tool

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Hi,

 

There is no direct option/switch for conversion of gated clocks in ISE. This feature is available in Vivado.

 

Refer to page 60 of the user guide for an example which shows how to convert gated clocks in the design http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/sim.pdf

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor venky699
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Registered: ‎06-28-2013

Re: How to enable the flop option in the ISE design Tool

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Deepika,

Is there any option in Synplify pro tool. Bcz in my design the clock gating was used in so many modules. if i wan t to change it will take time. Suggest me any other option if possible.

Regards,
Venkatesh.
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Xilinx Employee
Xilinx Employee
8,824 Views
Registered: ‎09-20-2012

Re: How to enable the flop option in the ISE design Tool

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Hi Venkatesh,

 

Is it not possible to move to vivado (as this tool has this feature)?

 

I guess there is some option by the name "Fix gated clocks" in syplify. But re-check this in their user guides.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor venky699
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Registered: ‎06-28-2013

Re: How to enable the flop option in the ISE design Tool

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Deepika,

Currently i am using the V6, Vivado will support from V7. So i can't use Vivado.
I have checked the option by the name "Fix gated clocks" in syplify, In my tool version(synplify/2012.03-SP2) i am not getting that option.

If possible suggest any other method.

Regards,
Venkatesh.
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Xilinx Employee
Xilinx Employee
8,801 Views
Registered: ‎09-20-2012

Re: How to enable the flop option in the ISE design Tool

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Hello Venkatesh,

 

In ISE, I guess there is not direct option as already mentioned, you need to manually change the gated clocks. 

Did you check Implementation options in synplify? There is a seperate tab for gated clock conversion by name GCC.

Hope that helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor venky699
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Registered: ‎06-28-2013

Re: How to enable the flop option in the ISE design Tool

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Deepika, 

 

     I have read the Synplify manual in that it was mention that there is GCC tab in that "Clock Conversion" option is not coming. I am getting the below options only.

 

gcc.jpg

 

by default option 3 (convert(fix), report all registers option ) is selecting.

 

Regards,

Venkatesh.

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Xilinx Employee
Xilinx Employee
13,201 Views
Registered: ‎09-20-2012

Re: How to enable the flop option in the ISE design Tool

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I guess you need to post this on synplify forums for more details.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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