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Observer
Observer
693 Views
Registered: ‎11-19-2017

How to encrypt Verilog code having `include

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Hi,

Say I have several Verilog files for a design block (i.e., my_block),

* my_block.v

* my_block_defines.v

* my_block_subA.v

* my_block_subB.v

Where 'my_block.v' has following code,

--------------------------------------------------------

`include "my_block_defines.v"

`include "my_block_subA.v"

`include "my_block_subB.v"

module my_block ( .....); .... .... endmodule

------------------------------------------------------

How the 'my_block.v' can be encrypted using 'encrypt' TCL command.

Of cource, I can merge all files to one and then apply 'encrypt' command.

But I am looking for a way to deal with a hierarchical Verilog code without merging all codes.

Thnaks.

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Observer
Observer
660 Views
Registered: ‎11-19-2017

Re: How to encrypt Verilog code having `include

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It means there is no way to encrypt a hierarchical design containing `include.

Thanks.

-----------

[Packaging a Design with Global Include Files]
The Vivado IDE supports designating Verilog or Verilog Header files as global `include
files to process before any other sources.
Note: This feature is not supported when packaging a custom IP.
After packaging, the Vivado tool treats global `include files as standard Verilog or Verilog
Header files.
To package a design that uses global ‘include files, you must modify the HDL to place the
`include statement at the top of any Verilog source file that references content from
another Verilog or Verilog header file.

View solution in original post

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2 Replies
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Xilinx Employee
Xilinx Employee
669 Views
Registered: ‎05-22-2018

Re: How to encrypt Verilog code having `include

Jump to solution
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Highlighted
Observer
Observer
661 Views
Registered: ‎11-19-2017

Re: How to encrypt Verilog code having `include

Jump to solution

It means there is no way to encrypt a hierarchical design containing `include.

Thanks.

-----------

[Packaging a Design with Global Include Files]
The Vivado IDE supports designating Verilog or Verilog Header files as global `include
files to process before any other sources.
Note: This feature is not supported when packaging a custom IP.
After packaging, the Vivado tool treats global `include files as standard Verilog or Verilog
Header files.
To package a design that uses global ‘include files, you must modify the HDL to place the
`include statement at the top of any Verilog source file that references content from
another Verilog or Verilog header file.

View solution in original post

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