04-13-2018 09:21 AM
I have a project that contains several VHDL files. One of the files is in "Unreferenced" limbo. The file checks syntax correctly, there are no errors or warnings. There is no indication, at all, anywhere, as to why the file is "Unreferenced".
What are the correct methods to figuring out how to deal with a file like this?
How do I get even a little clue from Vivado as to what it does not like?
Why is Vivado so reluctant to give out clues?
04-13-2018 10:35 AM
There are many root causes for this issue.
Can you share us a small testcase to regenerate this issue at our end? And what Vivado version are you using with Which OS?
04-17-2018 03:00 AM
This topic is still open and is waiting for you.
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If this is not solved/answered, please reply in the thread.
Thanks in advance and have a great day.