07-10-2018 06:55 PM
Hello Xilinx Support,
I hope this is right place for this kind of issue.
In our FPGA project we have many IPs, which takes a while to generate.
And we use git as a source control to keep our project.
Now each time we check in, checkout our Vivado project the IPs becomes out of data and Vivado asks for re-generation.
Previously we used to use dcp files from IP and add it to your project, in such case there was no need to regenerate IPs each time we checkout our project. However Vivado does not support this flow, because when we add dcp to Vivado it automatically does not add that file to design hierarchy.
Please let me know what Xilinx recommended way to resolve the issue.
07-11-2018 12:53 PM
07-13-2018 01:52 AM
When dealing with revision control, it is recommended to use script-based non-project mode.
Please read the Revision Control recommendations in this User Guide (UG892): https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug892-vivado-design-flows-overview.pdf
You may want to set the location of the source files and IP to Read-only. By having these sources files as read-only and stored somewhere else, they can easily be referenced from their managed read-only locations. If sources need to be modified, they
can be checked out into the local working area. This and other info can be found on page 84 of UG892: "Using Read-Only managed Source Directly".
Also check more info in relation to Revision Control in these User Guides:
Hope this helps.