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stemac00
Newbie
Newbie
504 Views
Registered: ‎05-04-2020

How to generate a succession of sums outside of a process

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Hi guys I'm new on the forum. I want to generate a succession of sums in vhdl like this:

Name : for k in 1 to precision generate

A <= A + shift_right(B,2*k-1) -shift_right(B,2*k);

end Generate;

But in this way it fails in implementation with error multiple driven pins. If I write all the succession manually it works but I need that the precision can be modified by a generic. Any advise?

Thanks

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calibra
Voyager
Voyager
468 Views
Registered: ‎06-20-2012
Name : for k in 1 to precision generate
N1:IF (k = 1) GENERATE
A(1) <= shift_right(B,2*k-1) -shift_right(B,2*k);
End generate N1;
N2:IF (k /= 1) GENERATE
A(k) <= A(k-1) + shift_right(B,2*k-1) -shift_right(B,2*k);
End generate N2; 
end Generate Name;
SUM <= A(precision) ;
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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@stemac00,

First piece of advice: "for" loops in RTL don't do what they do in software.  In software, a "for" loop will run something multiple times on successive time steps.  In RTL, N iterations created from a "for" loop will create N copies of the hardware described by the loop.  All of that hardware then operates on the same clock cycle.

This is probably not what you are interested in doing.

The other thing you are missing is the answer to the question: how does the data to get summed come into your core?  FPGAs are really good at streaming data.  If you want to sum a series of data values streamed into a core, then something like this might be closer to what you are looking for.

Dan

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calibra
Voyager
Voyager
473 Views
Registered: ‎06-20-2012

Why outside of a process ?

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calibra
Voyager
Voyager
469 Views
Registered: ‎06-20-2012
Name : for k in 1 to precision generate
N1:IF (k = 1) GENERATE
A(1) <= shift_right(B,2*k-1) -shift_right(B,2*k);
End generate N1;
N2:IF (k /= 1) GENERATE
A(k) <= A(k-1) + shift_right(B,2*k-1) -shift_right(B,2*k);
End generate N2; 
end Generate Name;
SUM <= A(precision) ;
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stemac00
Newbie
Newbie
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Registered: ‎05-04-2020

Outside a process because has to be an asynchronous module to implement a division by 3. I think that in this way it will work. Tomorrow I will try it. Thanks

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calibra
Voyager
Voyager
369 Views
Registered: ‎06-20-2012

A process can be also combinational or "asynchronous" as you said.

 

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