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Scholar
Scholar
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Registered: ‎12-07-2018

How to generate _t and _c differntial pairs in i/o planner for DDR4 Mem?

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Hello, I am adding DDR4 pins to my I/O Planner project. I am looking at a DDR4 example and I see the DDR4 diff pairs have _t and _c  appended to the Differential Signal, such as DDR4_sdram_dqs_t[0] and DDR4_sdram_dqs_c[0].  Normally it added only _N. 

 

How can I get it to do this?

 

Thanks,

Joe

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Scholar
Scholar
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Registered: ‎12-07-2018

Re: How to generate _t and _c differntial pairs in i/o planner for DDR4 Mem?

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I'm doing a simple example that is using a DDR4 IP module and I am having trouble matching the I/O of the DDR4 with the pins on the FPGA. The Interface Port on my Block Design is called PL_DDR4 and my schematic pins all have PL_DDR4 in their net names. I just know know how to get things to work.

 

Joe

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Scholar
Scholar
337 Views
Registered: ‎12-07-2018

Re: How to generate _t and _c differntial pairs in i/o planner for DDR4 Mem?

Jump to solution

I'm doing a simple example that is using a DDR4 IP module and I am having trouble matching the I/O of the DDR4 with the pins on the FPGA. The Interface Port on my Block Design is called PL_DDR4 and my schematic pins all have PL_DDR4 in their net names. I just know know how to get things to work.

 

Joe

View solution in original post

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Scholar
Scholar
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Registered: ‎12-07-2018

Re: How to generate _t and _c differntial pairs in i/o planner for DDR4 Mem?

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It turns out that all the I/O to the DDR4 module us containted in an Interface that is available when you get into IO Planner. Drop the list down of the Interface and you will see all the DDR4 I/O ports. Now you can place the ports to the BGA pins. Not much of a big deal. I was making it too hard. Joe

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