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rebakker
Participant
Participant
959 Views
Registered: ‎11-12-2014

How to include IP Integrator cores in a subdesign?

Hello,

I have created a design in VHDL using several files containing a hierarchy of enities, components, packages etc. This design is included within a Vivado Block Design as a Module. Besides the plain VHDL components in .vhd files, the hierarchyn also include an IP Integrator FIFO Generator core (distributed RAM).

When I add the .xci file to the Vivado Project Manager it reports an error:

 [filemgmt 56-328] Reference 's_ACQ' contains sub-design file 'K:/Work/PLD/UDAS/ip_repo/s_ACQ/ip/acq_afe_fifo/acq_afe_fifo.xci', which is configured for out-of-context synthesis. OOC sub-designs are not allowed in the reference. To change the setting, use TCL command: 'set_property generate_synth_checkpoint 0 [get_files acq_afe_fifo.xci]'.

So this is not the right way. Include the .dcp file instead results in another problem:

 

 [Project 1-863] The design checkpoint file K:/Work/PLD/UDAS/ip_repo/s_ACQ/ip/acq_afe_fifo/acq_afe_fifo.dcp was generated for a block design or an IP or BD by an out of context synthesis run and should not directly be used as a source in a Vivado flow to refer to an IP source.  As of 2017.1, the DCP from OOC runs will not contain XDC timing constraints because these are expected to be referred to by the IP .xci or .xcix file source. DCP files prior to 2017.1 will contain incorrect constraints because they were generated with default OOC clock period which will not likely match your top level clock constraints when used in the full design context. 

I use the 'OOC' implementation instead of the 'Global' implementation since I need the *_sim_netlist.vhdl file for simulation.

To overcome these problems I now use the .vhd file from the synth directory of the generated FIFO core, together with the fifo_generator_v13_2_vhsyn_rfs.vhd file from the hdl directory.

But how and which .xdc file should be used?

Or is there a different and better method of using IP Integrator core in subdesign modules?

Thanks.

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2 Replies
rebakker
Participant
Participant
926 Views
Registered: ‎11-12-2014

If I add the .xdc files of the generated IP core (in this case there are three: acq_afe_fifo.xdc, acq_afe_fifo_clocks.xdc and acq_afe_fifo_ooc.xdc) to the Vivado Hierarchy tab using constrs_1, right click and select Edit Constraints Set..., these should be part of the project.

To make a connection between the xdc files and the cells I need to update the SCOPED_TO_CELLS property of the xdc file. So I use the TCL command:

set_property SCOPED_TO_CELLS {{design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[1].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[2].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[3].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[4].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[5].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[6].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[7].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[8].data_serdes/C_acq_afe_fifo} {design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/frame_serdes/C_acq_afe_fifo}} [get_files acq_afe_fifo.xdc]

When synthesized the log however contains the following critical warning:

CRITICAL WARNING: [Designutils 20-1277] Could not find cell 'design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[1].data_serdes/C_acq_afe_fifo'. The XDC file K:/Work/PLD/UDAS/ip_repo/s_ACQ/ip/acq_afe_fifo/acq_afe_fifo.xdc will not be read for this cell.

But when the synthesized design is opened and get_cells is used to find the cells.

get_cells -hier -filter {NAME =~ */C_acq_afe_fifo }

They are all listed:

design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[1].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[2].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[3].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[4].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[5].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[6].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[7].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/Gen_DataSerdes[8].data_serdes/C_acq_afe_fifo design_sFPGA_i/s_ACQ_0/U0/AcqAfeInst/frame_serdes/C_acq_afe_fifo

Why can't these cells be found and are reported with a critical warning in the log?

What am I doing wrong here?

 

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rshekhaw
Xilinx Employee
Xilinx Employee
869 Views
Registered: ‎05-22-2018

Hi @rebakker ,

Please check this AR# link, might be helpful.

https://www.xilinx.com/support/answers/69690.html

Thanks,

Raj

 

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