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mxm1898
Visitor
Visitor
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Registered: ‎09-28-2019

How to incorporate custom intermediate AXI interface to memory (and properly set addresses and access in software)?

Hello all,

I'm new to this type of design and I'm attempting to incorporate an open-source project into my design: https://github.com/IAIK/memsec
I'm attempting to test this block by implementing it on a Zedboard, using a Zynq processor to control the memsec block and write to a BRAM and the on-chip HP0 slave interface. This is the block diagram I am currently using: 

bd.png

I then have the addresses set to:addresses.png

My question is - are these addresses OK? And when I write code for the Zynq processor in Vitis, how would I access the BRAM and the HP0 interface? Basically I write to address 0x40000000 but I'm not sure if that is actually going to the HP0 interface or not. I'm also looking at the memory in the debugger and the BRAM address 0xC000000 doesn't even exist. In xparamters.h 0xC000000 doesn't even show up anywhere, and it doesn't appear in the linker script. I think I might be a bit confused about how this should be working.

Any insight would be very appreciated! Thanks!

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markgraf
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Registered: ‎04-04-2018

M_AXI_GP0 can access address' in the 40000000-7FFFFFFF range. I think you BRAM needs to be in that range. To access the DDR, through the MEMSEC, I think you would need to write to a BRAM, then use a DMA to move the data to the DDR.

Refer to section 4.1 of UG585 for system address map.
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com