How to indentify if IOB Flip Flop was used after P&R (Vivado 2018, Spartan7) ?

[juzl]

Hi,

I have found that non of proposed methods:

https://www.xilinx.com/support/answers/62661.html

to identify if IOB FlipFlop is in use does not work for my flow (Vivado 2018.2.1, Spartan7).

Method 1: (to see *_io_placed.rpt) is evidently obsolate since there  is no column "IOB Sequential Element"

Method 2: use ultrafast script, does not support Spartan7

I cannot find alternative, except looking into implemented device manually.

thanx
Peter

[markg@prosensing.com]

Hi Peter,

According to the AR, only the report_datasheet method should work for Vivado v2018.2.  I can confirm that it doesn’t work in v2018.3.

The Vivado menu, (Edit > Find), has a good search tool, which also shows the Tcl command corresponding to the search parameters you selected.  Below is a Tcl command that the search tool generated for me.  It seems to find all registers that I packed into the IOB.

show_objects  [get_cells -hierarchical -filter {IOB == "TRUE" && IS_LOC_FIXED == "TRUE" && PRIMITIVE_TYPE =~ FLOP_LATCH.*.*} ]

Cheers,
Mark

[juzl]

Thank you Mark,

script works!

However I still do not understand why is this, often essential information, not part of I/O report?

Is this gona change in near future releases?

I mean it was in reports for decades (for good reason) why not anymore?

thanx

Peter

[markg@prosensing.com]

Peter,

Good questions. 

Hopefully the people from Xilinx who monitor the Forum will notice this problem and submit a change request.

You can help by going to the AR that you mentioned and responding with "NO" to "Was this Answer Record helpful?" - and type into the response box that the report_datasheet method is not working in Vivado v2018.2.  I just did this too.

Mark

[juzl]

Yep, I did it even prior this forum entry, however I have feeling that Xilinx make 1 step forward and 2 steps back. Just wondering what is the cause.

[drjohnsmith]

Re why Xilix obscue this,

   cause they run only by TCL,  and are aiming at th ebig projects, goign to ASIC , where IOB is not a question.

Used to be reported in th eclear, but now days ,

   if in doubt,  the answer to any questoin is

a) run an IBIS model

or

b) run a TCL command

sorry,

not much chance of xilxin listening to any change,

hay its hard enough to the the regsister to be forced into an IOB,

    which used to be so easy,

[graces]

The method described in section "In Vivado versions starting from 2015.3:" in the AR should work.

i.e. run "report_datasheet -name xxx" in GUI to generate a datasheet report that contains the IO Reg Type column.

[juzl · Accepted solution]

I confirm that TCL "report_datasheet -name XXX" works.

Thank you,

Peter

[markg@prosensing.com]

@graces 

In Vivado V2018.3, whether I run "report_datasheet -name xxx" from GUI (Reports > Timing > Report Datasheet) or from Tcl Console, the "(IOB)" marker is not appearing in the report (when it should).  Also not working for me is the AR62661 suggestion "generating the report_timing_summary report with the "Report Datasheet" option checked."

In the above screenshot of the datasheet report, the properties box for register, DGOUT_J19_reg[0], shows it to be fixed in the IOB but the marker, "(IOB)", is missing from datasheet report.

Thanks,
Mark

[graces]

markg@prosensing.com 

I think the value 'FDRE(IO)' signifies an SDR FF placed into IOB. Otherwise it would be 'FDRE'.

[markg@prosensing.com]

@graces 

For Vivado V2018.3, I does appear that report_datasheet tagging is now "(IO)" instead of "(IOB)" as described in AR#62661.  I hope that Xilinx will update AR#62661 with this information.

Thanks,
Mark