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Visitor
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Registered: ‎02-08-2017

How to integrate BUFGMUX in IP Integrator?

Hello Forum,

 

I am trying to do something that should be really simple, but is proving to be quite difficult.  Hopefully someone can help.

 

First, a few of my operating constraints that I can't change for this project:

  • Vivado 2015.2
  • Out of context (OOC) build
  • Using block design .tcl file as my top level source file
  • Using scripted build in project mode

 

I require the use of a BUFGMUX in my block design.  Unfortunately, the Utility Buffer IP block in Xilinx does not include this type of primitive.  So I created my own IP block, which was simply a VHDL file that instantiates a BUFGMUX.  I added some custom IP packaging commands using the ipx:: TCL library, which allowed me to specify that I had clock inputs and clock outputs and to set the frequency of the output clock (otherwise it defaults to 100 MHz).  I connected my new IP and the block design validates without errors or critical warnings.

 

However, when I go to actually build the design I am getting an error during the implementation stage because my downstream components that are clocked by the output of this BUFGMUX IP block have their own BUFG's on the input clocks and it is not valid to drive a non-muxed BUFG with another BUFG.  

 

So the tool recognizes the fact that my IP contains a BUFG, but I think it doesn't do it before it has already added BUFGs to the other IP blocks in the system.  However, when I use the Clocking Wizard IP and generate clocks with BUFG outputs, the tool does not add additional buffers to the downstream devices.  Perhaps this is an issue of built-in vs. user IP blocks then, but it says there is a way to notify the rest of the block design that there are buffers attached to clock lines already.

 

Thank you,

 

Scott

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3 Replies
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Moderator
Moderator
2,566 Views
Registered: ‎11-09-2015

Hi @saconnors,

 

You can try to use the synthesis attribute CLOCK_BUFFER_TYPE set to none in your RTL before packaging your IP.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎02-08-2017

Hi @florentw,

 

Thank you for your suggestion.  I was able to add BUFFER_TYPE constraints to an OOC .xdc file for the affected clock ports for each of the custom IP blocks in my design that are being driven from the output of the BUFGMUX IP.  So it is a viable workaround for my problem.

 

However, it was painful (I have dozens of IP blocks connected to this clock) and it also leads to a maintenance headache down the road whenever I add a new IP connected to this clock.  I was hoping that there would be a way to tell the tool that the output of my BUFGMUX IP was already driven by a BUFG, so not to add more BUFGs in downstream IP.  This is how the Clocking Wizard or the built-in Utility Buffer BUFG must work, so how can the same thing be done with my custom IP?  

 

Scott

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Moderator
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Registered: ‎11-09-2015

Hi @saconnors,

 

Just write BUFFER_TYPE to your RTL instead of you xdc, this way it is only once per IP (not per instance)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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