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nanson
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Registered: ‎08-31-2017

How to integrate an AXI slave IP with Zynq Ultrascale+ MPSOC in Vivado IP Integrator

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Hi, dear elites,

Previously, I'm the user of Zybo and PYNQ-Z1/2 which uses ZYNQ7 Processing System as processor IP. It's ok for me to integrate the customized or additional AXI-slave IP in the Vivado IP Integrator in GUI mode. 

Now, we need to retarget our same AXI slave design to ZCU-104 which uses Xilinx Ultrascale+ MPSOC. However, I'm not familiar with Xilinx Ultrascale+ MPSOC and am looking for a tutorial or reference in how to integrate an AXI IP with Xilinx Ultrascale+ MPSOC macro in Vivado IP Integrator.

Would you please point me where I can learn how to integrate AXI slave IP with Xilinx Ultrascale+ MPSOC macro in Vivado IP Integrator? The AXI Slave IP I uses only has an AXI slave interface with an AXI clock. 

Thank you

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tedbooth
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Registered: ‎03-28-2016

@nanson 

The Zynq US+ processor subsystem (PS) allows the user to specify up to 4 clocks that can be provided to the programmable logic (PL).  By default, when the PS block is dropped onto the IPI canvas, it has the pl_clk0 enabled and set to 100 MHz.

You can change the clock speed of pl_clk0 or enable additional clocks by "Recustomizing" the Zynq PS block.  Double click on the block to open the "Re-customize IP" window.  Select "Clock Configuration" -> "Output Clocks" -> "Low Power Domain Clocks" -> "Pl Fabric Clocks".  From there you can make changes as needed.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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tedbooth
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Registered: ‎03-28-2016

@nanson 

The process of building an embedded design in IPI for Zynq US+ is very similar to the process for the Zynq-7000.  Here is link to a tutorial that might be helpful.  Chapter 6 deals with system development in IPI.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1209-embedded-design-tutorial.pdf

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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nanson
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Registered: ‎08-31-2017

@tedbooth

Thank you.

I have one more question. In the  Zynq Ultrascale+ MPSOC macro, it generates a clock signal pl_clk0 for PL use. Do you know the frequency of the clock signal pl_clk0  output from the Zynq Ultrascale+ MPSOC macro? I need to set the corresponding synthesis constraint for the AXI Slave IP in the PL side.

 

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tedbooth
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Registered: ‎03-28-2016

@nanson 

The Zynq US+ processor subsystem (PS) allows the user to specify up to 4 clocks that can be provided to the programmable logic (PL).  By default, when the PS block is dropped onto the IPI canvas, it has the pl_clk0 enabled and set to 100 MHz.

You can change the clock speed of pl_clk0 or enable additional clocks by "Recustomizing" the Zynq PS block.  Double click on the block to open the "Re-customize IP" window.  Select "Clock Configuration" -> "Output Clocks" -> "Low Power Domain Clocks" -> "Pl Fabric Clocks".  From there you can make changes as needed.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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