06-19-2015 03:55 AM
I initialized the block memory with coe file to use it as single port ROM in standalone mode. So, the data width of ROM is 32 bits and depth of 62000(this would need 16 bit address for reading). AXI BRAM controller was instantiated in Block design and data width was set to 32.
But upon synthesis, I get following error
[BD 41-1228] Width mismatch when connecting input pin '/blk_mem_gen_0/addra'(16) to net 'axi_bram_ctrl_0_bram_addr_a'(14) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
So, the problem is BRAM controller 's interface which has bram_addr_a of only 14 bits. This is strange. I don't know how bram_addr_a width is determined?
06-20-2015 05:06 PM - edited 06-20-2015 05:06 PM
Are you sure you have 62000 x 32-bits in your coe and not just 62000 bytes? That could explain the 2-bit difference. 8-bit bytes versus 32-bit words.
I tried this with Block Memory Generator 8.2 (Vivado 2015.1) and looks ok. Setting up a Single-Port ROM with 32 width and 62000 depth shows addres Width A: 16 in the Summary and the generated files show 16 bit address as well:
06-26-2015 01:50 AM
06-29-2015 10:29 AM
I see. Did you notice the data busses out of the BRAM controller are 32-bits? The S_AXI bus would have a 32-bit interface as well since that is the narrowest an AXI bus can be. You could arrange your data in 32-bits in the Block Memory Generator and when you do a narrow read on the S_AXI interface you should get the right 16 bits back.
06-30-2015 01:05 AM
@bisector. Yes, I know that data_bus out of BRAM controller are 32 bits. The S_AXI bus too will have 32 bit interface. I tried with 32 bits in Block memory generator(effectively only 16 out of 32 bits will be used as my data is 16 bits). But this will not solve the issue of address.
The BRAM controller's bram_addr_a could be changed by changing the Data width in Recustomize IP GUI. The default is 32 bit data width. And the bram_addr_a for this 32 bit wide data width is 15 bits(which is not enough address as my block memory generator has over 60000 data. This means I need at least 16 bit address to read those 60000.).
This means I cannot change the default(32 bit) data width of bram_ctrl, and this would create 15 bit bram_addr_a. And this 15 bit bram_addr_a conflicts with 16 bits Block memory generator's addra.
07-03-2015 09:49 AM
Have you tried actually reading something with the 32-bit wide data width and 15 bits of address? I assume you would get 32-bits back then for each address, two 16-bit values in each 32-bit word location.
08-21-2015 04:58 PM
Your controller has 32-bit data width.
Your Bram has 16-bit.
Your controller will be accessing the BRAM in 2-byte increments, therefore you have that 1-bit mismatch. You will need to tie controller bits 14:0 to BRAM 15:1, and tie BRAM 0 to ground, because, in effect, the controller will only be accessing even BRAM locations.
One more thing to consider is that to write to the BRAM you will need to enable byte-writes on the BRAM or implement your own external control method so that the writes to not adversely affect other data.
Easiest thing to do is use 32-bit data widths for the BRAM. Remeber that you can always configure PORTB to be another data width. To do this you will need to configure the BRAM as native interface and make sure the side connected to the BRAM controller has no registers enabled.