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joe306
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Registered: ‎12-07-2018

How to make a pin to be Differential LVDS?

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Hello, I am a newbie and need some help making an input pin to be LVDS. I have added a input pin to my Block Design and have run the "Run Implementation" tool and I do see my pin in the list of Scalar Port. I have made the IO Std to LVDS. I thought it would create a _p and _n signal on the name of my pin "PL_LOC_REF_CLK". Can someone help me please?

 

Thank you,

Joe

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jg_bds
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Registered: ‎02-01-2013

 

Ordinarilly, one uses a Clocking Wizard to bring a clock into a Block Design. The configuration of the Clocking Wizard can select a differential input for the clock reference:

2019-09-21_22-29-30.jpg

That will change the input port of the Clocking Wizard block to a differential port, which you can connect to a differential input clock port of your BD:

2019-09-21_22-34-41.jpg

You can assign the I/O Std to "LVDS" in the Synthesized, when you assign the package pin.

You really only assign the P-side package pin; the N-side package pin gets inferred based on the location of the P pin.

2019-09-21_22-41-23.jpg

-Joe G.

 

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joe306
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Registered: ‎12-07-2018

Here is a  screen shot.

 

Xilinx.jpg

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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @joe306 ,

So you are trying to convert single ended signal to differential signal.

You can convert probably any single ended signal into a differential ouput signal by using OBUFDS primitive.

Things to keep in mind:

1. The differential ouput signals must exit only to the top level IOB pads.

2. Choose the proper pin polarity in the constraint file when defining the pins.

 

I have attached a PDF file to give more info about LVDS standard. For your application, I believe LVDS_25 standard should be good.

 

Heres an example of converting a single ended standard to a differential ended:

 

OBUFDS #(
      .IOSTANDARD("LVDS_25") // Specify the output I/O standard
   ) OBUFDS_inst (
      .O(ServoDataToSOCp),     // Diff_p output (connect directly to top-level port) (p type differential o/p)
      .OB(ServoDataToSOCn),   // Diff_n output (connect directly to top-level port) (n type differential o/p)
      .I(Servo_Data)      // Buffer input (this is the single ended standard)
   );

Thanks,

Raj

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joe306
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Registered: ‎12-07-2018

Hello, thank you for responding to my message. My input clock is a differential LVDS input. How to I set that up in the Block Design or do I do that in the I/O Packager window that I showed above? In Quartus I would go to the Pin Planner find the name of the port and choose LVDS, it would then create a net with _p and _n appended to the name of the net in the the Block Design. I could then assign the differntial pairs to the BGA pin. I just don't know how to do differntial inputs in Vivado. I am using the Block Design to enter in my modules and I/O pins. 

 

Thank you,

Joe

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jg_bds
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Scholar
1,814 Views
Registered: ‎02-01-2013

 

Ordinarilly, one uses a Clocking Wizard to bring a clock into a Block Design. The configuration of the Clocking Wizard can select a differential input for the clock reference:

2019-09-21_22-29-30.jpg

That will change the input port of the Clocking Wizard block to a differential port, which you can connect to a differential input clock port of your BD:

2019-09-21_22-34-41.jpg

You can assign the I/O Std to "LVDS" in the Synthesized, when you assign the package pin.

You really only assign the P-side package pin; the N-side package pin gets inferred based on the location of the P pin.

2019-09-21_22-41-23.jpg

-Joe G.

 

View solution in original post

joe306
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Registered: ‎12-07-2018

Hello, thank you very much, this is exactly what I needed to see. I will give it a try and get back with you.

 

Respectfully,

Joe

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