07-09-2019 02:05 AM
How can I generate verilog HDL code from an IP core component.
For example I am working with fir filter so I create a design by selecting FIR_COMPILER component from IP catalog, provide the required coefficient values and generate main module and test bench from it. But the main module and test bench code generated is in VHDL not in verilog. I am trying to change it into verilog but not able to do.
Please help with this.
Waiting for thr reply at the earliest.
07-09-2019 02:21 AM
07-09-2019 02:34 AM
07-09-2019 02:37 AM
So for all the components present in IP catalog verilog code cannot be generated or is it only for FIR_COMPILER component.
07-09-2019 02:39 AM
07-09-2019 02:41 AM
Hi @kp1998_ ,
Thie information i shared was specific for FIR COMPILER. If in your BD there are other different blocks and in then if there are Xilinx IP blocks, you can check the Table as mentioned for FIR, in User guide of that IP whether Verilog is mentioned or VHDL is mentioned or both are mentioned.
07-09-2019 03:12 AM
07-09-2019 08:33 PM
Ok Can u please share that user guide, will be of great help
You can search for the IP "Product Guide" on xilixn.com by searching the IP name.
07-10-2019 12:57 AM
Which language being used for the IP really doesn't matter, unless that your simulator does not support mixed language simulation.
The IP is provided as a package. It comes with the instantiation template, GUI customization wizard, Product Guide for the interface and function details. You don't need to read the IP code.
I'm afraid most of the IPs come with VHDL.
What is your concern of using VHDL for the IP?