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Adventurer
Adventurer
433 Views
Registered: ‎06-07-2012

How to package a SystemVerilog simulation package with a VHDL IP.

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Hi,

I am trying to package the simulation model files with my VHDL source files to create a nice self-enclosed IP. This used to work like magic few weeks ago, but I just ran out of magic after repackaging my IP.  I'd like understand how it works to track what I am doing wrong.

The SystemVerilog file I can be seen here (the very short cleaned version):

// File CIPUDP_framer.sv
package CIPUDP_framerPkg;
   
class CIPUDP_framer;
   
endclass
endpackage

I have tried many way to include that file and none worked. Here is my latest trial:

filegroupe.JPGHere is what gets in the .XML:

<spirit:name>sim/CIPUDP_framer.sv</spirit:name>
<spirit:fileType>systemVerilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
<spirit:logicalName>work</spirit:logicalName>

After I packaged the IP, I go back to my actual project in Vivado, which see the new IP. I upgrade the IP and generate all output products.

The SystemVerilog got copied into source directory of my project, along the .VHD files:

MYPROJECT.srcs\sources_1\bd\MY_BD_NAME\ipshared\36db\ 

There I find the HDL subdirectory with the IP implementation source code and the SIM directory with my simulation model in .SV. The IP implementation code got also copied under:

MYPROJECT.ip_user_files\bd\MY_BD_NAME\ipshared\36db\HDL 

However the /SIM isn't copied in that ip_user_files directory. This looks like the source of my problem.

After that, whenever I try to simulation with Vivado (XSIM), the package from my .SV file isn't found:

ERROR: [VRFC 10-2989] 'CIPUDP_framerPkg' is not declared [C:/PROJECT_DIR/testbench/Cnet_ip.sv:15]

What would be the proper way to package a SystemVerilog simulation Package file into an IP with the IP packager?

Thank you for any pointers,

jf

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1 Solution

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Adventurer
Adventurer
175 Views
Registered: ‎06-07-2012

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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I built a testcase from scratch... and the magic came back and it works as expected !?

 

So I'll keep my testcase close and if I run out of magic again, I'll compare my project to my working testcase.

 

I'll report back if I ever find something.

 

Best Regards,

 

jf

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7 Replies
Moderator
Moderator
376 Views
Registered: ‎05-31-2017

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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Hi @jlarin ,

Can you make sure the project simulates without any errors before packaging ?

Also, you need to make sure that CIPUDP_framer.sv file gets compiled before Cnet_ip.sv file.

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Adventurer
Adventurer
352 Views
Registered: ‎06-07-2012

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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Hi @shameera ,

Yes the main project compiles (there is no syntax error). In fact, I just added the CIPUDP_framer.sv as a simulation source into the main project and everything simulates correctly. 

If you asked if the packaging IP project simulated, then yes it did, but it does not uses the .SV file.  I normally don't simulate by itself the IP I package.  I just check that everything compiles, but since there are no testbench in the IP project, XSIM only elaborates the IP top. So at that point, the .SV file is never called.

The main purpose of my initial question is that I shouldn't have to add manually the .SV source helper file to the main project. When I add the IP in the block diagram, it is added as a single unit and all VHD source files are automatically added to the project.  Then to simulate the IP, I shouldn't have to go inside the IP directory to add somes files to the simulation.

To fix that, I am looking for an example or documentation (other than UG1118) that shows what are the best practice to include a simulation helper .SV file with a VHDL IP, OR a way to debug why the file is not automatically included.  

Thank you for looking into this issue,

 

jf

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Moderator
Moderator
336 Views
Registered: ‎05-31-2017

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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Hi @jlarin ,

From your last post, my understanding is as follows

1.The packaged IP compiles filne and it does not use the .sv file as it does not have the testbench.

2.You are willing to package the .sv file with your IP, for simulation purpose alone .

3.In the main project you want to use the .sv file packaged with the IP in the testbench file Cnet_ip.sv

 

Please let me know if the above understanding is not clear.

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Adventurer
Adventurer
308 Views
Registered: ‎06-07-2012

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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@shameera wrote:

From your last post, my understanding is as follows

1.The packaged IP compiles filne and it does not use the .sv file as it does not have the testbench.

2.You are willing to package the .sv file with your IP, for simulation purpose alone .

3.In the main project you want to use the .sv file packaged with the IP in the testbench file Cnet_ip.sv

 


Hi @shameera ,

Yes you described perfectly what I am trying to do.

Thank you for looking into this,

 

jf

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Moderator
Moderator
264 Views
Registered: ‎05-31-2017

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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Hi @jlarin ,

Can you please share us a small test case showing this behaviour, this would help us to easily debug further ?

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Adventurer
Adventurer
259 Views
Registered: ‎06-07-2012

Re: How to package a SystemVerilog simulation package with a VHDL IP.

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Hi @shameera ,

 

My question was twofold:  is there any documentation of the best practices on how to package IP with mixed language source code (beside UG1118 which does not cover that, AFAIK),

and,

how to debug that issue?

From your answer, I understand that there isn't readily available documentation on that subject, so I'll start building a test case (it shouldn't be difficult) and I'll submit it in this forum.

Thanks,

jf

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Adventurer
Adventurer
176 Views
Registered: ‎06-07-2012

Re: How to package a SystemVerilog simulation package with a VHDL IP.

Jump to solution

I built a testcase from scratch... and the magic came back and it works as expected !?

 

So I'll keep my testcase close and if I run out of magic again, I'll compare my project to my working testcase.

 

I'll report back if I ever find something.

 

Best Regards,

 

jf

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