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Scholar wzab
Scholar
7,191 Views
Registered: ‎08-24-2011

How to pass parameter to a nested IP core (and force its regeneration), basing on the parameter customized in my IP core?

Hi,

During development of my packaged IP core I have faced an iteresting problem.

I'll try to present it basing on a trivial core which shows the problem.

 

Let's assume, that I want to have a FIFO, which stores the structured information.

To keep it as simple as possible, let's assume that it stores infromation consisting of two fields:

key and payload.

The typical implementation may be as shown below:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;

-------------------------------------------------------------------------------

entity xqueue is
  generic (
    PAYLOAD_WIDTH : integer := 18);
  port (
    payload_in  : in std_logic_vector(PAYLOAD_WIDTH-1 downto 0);
    key_in :  in std_logic_vector(7 downto 0);
    payload_out  : out std_logic_vector(PAYLOAD_WIDTH-1 downto 0);
    key_out :  out std_logic_vector(7 downto 0);

    clk : in STD_LOGIC;
    srst : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    full : out STD_LOGIC;
    empty : out STD_LOGIC);
    
end xqueue;

-------------------------------------------------------------------------------

architecture beh2 of xqueue is

  signal din : STD_LOGIC_VECTOR ( PAYLOAD_WIDTH+7 downto 0 );
  signal dout : STD_LOGIC_VECTOR ( PAYLOAD_WIDTH+7 downto 0 );

begin  -- beh1

  din <= key_in & payload_in;
  key_out <= dout(PAYLOAD_WIDTH+7 downto PAYLOAD_WIDTH);
  payload_out <= dout(PAYLOAD_WIDTH-1 downto 0);
  
  fifo_generator_0_1: entity work.fifo_generator_0
    port map (
      clk   => clk,
      srst  => srst,
      din   => din,
      wr_en => wr_en,
      rd_en => rd_en,
      dout  => dout,
      full  => full,
      empty => empty);
  
end beh2;

Of course I can package this core, and it will contain the standard Xilinx IP core genrated by the FIFO generator.

The PAYLOAD_LENGTH parameter may be customized in a xgui of my component, but how can I pass it to the nested fifo_generator_0 IP core, so that its word width is automatically adjusted to PAYLOAD_LENGTH+8 ?

 

I've browsed docs related to the IP packager, and working with IP cores (UG1118, UG1119, UG896), but it seems that such a problem is not addressed here...

 

Thank you in advance for any advise.

With best regards,

Wojtek

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3 Replies
Xilinx Employee
Xilinx Employee
7,175 Views
Registered: ‎09-20-2012

Re: How to pass parameter to a nested IP core (and force its regeneration), basing on the parameter customized in my IP core?

Hi @wzab

 

It is not possible to pass parameters to nested IP core.

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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Scholar wzab
Scholar
7,164 Views
Registered: ‎08-24-2011

Re: How to pass parameter to a nested IP core (and force its regeneration), basing on the parameter customized in my IP core?

So the only option to have e.g., parametrizable width of the queue is to use inferrence?

I think that it would be really nice to provide possibility of passing such parameter form the "upper" IP core to the nested one and have it OOC resythesized when the OOC run for the "upper" IP core is started...

 

Thanks,

Wojtek

 

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Historian
Historian
7,155 Views
Registered: ‎01-23-2009

Re: How to pass parameter to a nested IP core (and force its regeneration), basing on the parameter customized in my IP core?

While not a "general" solution to this problem. Xilinx has recently introduced some new "MACRO" cells in the library. These can be instantiated and paramaterized. For the example you give, you can use the FIFO_DUALCLOCK_MACRO.

 

A number of MACROs exist that allow for paramaterizable instantiation of logic that map to RAMB, FIFO and DSP48E1 cells.

 

You can see them in the Libraries Guide (UG768).

 

Avrum