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Observer
Observer
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Registered: ‎06-22-2018

How to properly include systemverilog files

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[Linux, Vivado 2019.1]

Hello,

I'm trying to make a use of SystemVerilog interfaces. I was given several i/f files with .sv extention and I've created a project including them. Later on I would like to package my code into IPcore.
Generally I've terrible time including those files to projects, moreover - recently I've tried adding classes in .sv files and it was the same, but somehow I'd succeded

Whenever I add a SystemVerilog it is very likely to disappear from "Sources-Hierarchy" window and pop up again in "Unrefferenced files" category. So I've tried adding them via command:

set_property include_dirs <directory_pat> [current_fileset]

but the .sv file ends up in Non-module Files and/or Verilog Header. Probably this is no good for me too, since after "somehow" successfully packaging the IPcore, the interface is not utilized: i cannot refer to it in code by it's name...

Can anyone please tell me how to include SystemVerilog files in Vivado effectively? I did it once or twice but it was really random...

And one more thing - I know that Verilog does not allow unpacked arrays as input/output signals to modules. However it's legal in SysVeri. When Vivado is sythesising the design it flattens the unpacked array to vector and some type mismatches may occure. The solution for this problem (according to support) is to run global sythesis. My question is: how to set "global synthesis" parameter for .sv file? It's not an IPcore... .

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Observer
Observer
347 Views
Registered: ‎06-22-2018

Solved,

For some reason I needed to create a new file and copy the code into it. Thank-you-Vivado :')

If it comes to arrays - I've switched to packed...

View solution in original post

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Highlighted
Observer
Observer
348 Views
Registered: ‎06-22-2018

Solved,

For some reason I needed to create a new file and copy the code into it. Thank-you-Vivado :')

If it comes to arrays - I've switched to packed...

View solution in original post

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