07-22-2019 10:04 AM
I'm evaluating a soft-core processor design in an Arty A7 development board, and I'm having trouble connecting a UART to the processor's "Peripheral Port" because since I'm not using a Microblaze, I am unable to set the address of the peripheral via the Address Editor.
The processor is a Sifive E31 and has an AHB peripheral port that I connect to with the ahblite axi bridge, and then through an axi interconnect, I hang a UARTlite peripheral. The peripheral port is discussed more here: https://static.dev.sifive.com/E31-RISCVCoreIP.pdf
What I'm having a hard time understanding at the moment is how to give my "axi_uartlite_0" an address? In processor space the peripheral port can be accessed from 0x20000000->0x3FFFFFFF, and I'd like to set the uart peripheral at the beginning at 0x20000000. However, since my E31_Top object does not seem to "expose an AHB master port" I am not able to set the address ranges.
The peripheral bus from the core looks like:
.periph_port_ahb_0_hmastlock(0), .periph_port_ahb_0_htrans(m_ahb_htrans), .periph_port_ahb_0_hsel(m_ahb_hsel), .periph_port_ahb_0_hready(m_ahb_hready_in), .periph_port_ahb_0_hwrite(m_ahb_hwrite), .periph_port_ahb_0_haddr(m_ahb_haddr), .periph_port_ahb_0_hsize(m_ahb_hsize), .periph_port_ahb_0_hburst(m_ahb_hburst), .periph_port_ahb_0_hprot(m_ahb_hprot), .periph_port_ahb_0_hwdata(m_ahb_hwdata), .periph_port_ahb_0_hreadyout(m_ahb_hready_out), .periph_port_ahb_0_hresp(m_ahb_hresp), .periph_port_ahb_0_hrdata(m_ahb_hrdata),
And all of the signals inside are exposed at the top level. How do I proceed from here?
07-25-2019 06:30 AM
Are you sure you do not have the address editor tab? Even if you click Window > Address editor
The address editor is usually used to do the routing of the interconnect and as you have an AXI interconnect I would expect that you have the address editor tab available
07-25-2019 07:55 AM
Yes, even Window->Address Editor is greyed out. Documentation seems to specify that there needs to be at least one AXI master for the address editor to be available, which I guess is true for the AXI Interconnect... Would I need to layout the port on my RTL block differently to allow it to be recognized as a master?
I've attach an image of the unavailability of the address editor with an open design.
07-29-2019 07:46 AM
I did some test, doing the same kind of design. I am able to get the Address Editor Tab in IP integrator using a similar design as yours:
One thing that could explain this: did you run validate bd design? This should propagate the AXI parameters and the address editor tab should appear
08-07-2019 01:09 PM
Yes, I've made sure the design is validated (passes with "Validation successful. There are no errors or critical warnings in this design"), but I still do not have the address editor available.
08-08-2019 11:13 PM
08-11-2019 01:10 PM
Yes, of course, the project is attached. I had to run a "reset_project" command to get the directory small enough to attach, hope that didn't cause any issues. It was built on Vivado 2017.4, but was also tested on 2019.1 (with IP upgrades) to test if it was a version issue.
08-21-2019 01:07 AM
Thank you for sharing your project.
I tried on my machine with 2019.1 and I found a weird behaviour. If I just replace the AHB-Lite to AXI Bridge with the same configuration (I used copy/paste un IPI) and with the same connection, then I can see the address editor tab...