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Adventurer
Adventurer
10,479 Views
Registered: ‎03-02-2010

How to use Core Generator cores?

Using 9.2i.

 

I have made a core using core generator. I want to use it my ISE project. I have one verilog source file in my project which needs the function of the core made core gen. How can I do this? I have tried to copy the ngc, veo, and v files from the core gen project dir to my ISE project dir. Then I 

 

 instantiated the core in my design in the line where I needed to use the functionality of the core by: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p);  but I still cannot compile and therefore cannot synthesize my design.

 

Please provide step-by-step direction on how to do this (instantiate for synthesis).

 

Thank you. 

 

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7 Replies
Xilinx Employee
Xilinx Employee
10,472 Views
Registered: ‎08-13-2007

Re: How to use Core Generator cores?

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Adventurer
Adventurer
10,463 Views
Registered: ‎03-02-2010

Re: How to use Core Generator cores?

After consulting those, I see that I was using core gen to make the modules separately. Now when I create a core gen module from within my ISE project, it gets added to my design project automatically and I can synthesize my design.

 

But, I wanted a structural description of the core gen module I created. It doesnt seem you can choose this option within ISE, other than from Core Generator itself outside of the ISE project. When I added the .xco file of the module made outside of my ISE project and try to synthesize, I get no errors. But I notice that my logic utilization dropped substantially. When I made the module from within my ISE project (pipeline divider) I use around 2000 slices. When I make the module outside of ISE and add the .xco file later, I'm only using about 200 slices. Whats happening here? 

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Xilinx Employee
Xilinx Employee
10,458 Views
Registered: ‎08-13-2007

Re: How to use Core Generator cores?

Unclear based on the information provided...

Did you configure the cores the same? (it might help to diff the xco files)

Is the rest of the design the same?

Are you comparing the same utilization #s (e.g. not the par report with the synthesis report)?

 

The management of the cores inside or outside ProjNav is a flow difference (there are tradeoffs) but should generally end up with the same result.,

 

 

/*

But, I wanted a structural description of the core gen module I created.

*/

I don't understand what you mean here.

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Adventurer
Adventurer
10,443 Views
Registered: ‎03-02-2010

Re: How to use Core Generator cores?


timpe wrote:

  /*

But, I wanted a structural description of the core gen module I created.

*/

I don't understand what you mean here.


ProNav cannot simulate the pipeline divider without the structural description. Therefore, I had to use Core Generator to make the pipeline divider core with a structural description so I can simulate the design within ProNav. The description provided for the divider core when made within ProNav is behavioral.....this is the only reason why I'm using core generator.
 
The design is absolutely the same (for core and ProNav) . All I did was change the core name to the new core name when I instantiated it in my main verilog module. I of course added the new .xco file to my ProNav project before synthesizing. When I compare the post-synthesis logic utilization for both scenarios, it is very low when I generate the core outside of ProNav using core generator. I chose the Verilog design flow with ISE in Core Generator.

 

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Xilinx Employee
Xilinx Employee
10,439 Views
Registered: ‎08-13-2007

Re: How to use Core Generator cores?

I still don't understand "behavioral" versus "structural" in this context though I understand what they mean in general.

I'm assuming you are using the Pipelined Divider 3.0 in 9.2i.

 

You should look carefully through the output files:

[designname]_readme.txt - description of the files

 

The ngc file is the synthesized netlist. This should generally not affect the synthesis resource estimate as the core is a black-box and later meged via ngdbuild (translate) and map into your design.

 

ProjNav does not do any simulation, though it can call ISIM or ModelSim to do this for you from the IDE. It isn't clear why you couldn't simulate it from the functional model.

 

The functional simulation model (e.g. .v) will parameterize your configuration of the core to the base core simulation model in XilinxCoreLib. This is not intended to be synthesized - it is for simulation only. This is not a structural description. It is possible to generate one (specific configuration of elements like LUT4s and FFs from the netlist) but you generally shouldn't need to.

 

The instantiation example (e.g. .veo) shows you how to instantiate it in your design.

 

I would carefully compare/diff your synthesis reports to see what is different in your case.

bt

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Adventurer
Adventurer
10,435 Views
Registered: ‎03-02-2010

Re: How to use Core Generator cores?

Okay, this here is the situation.

 

 

ERROR:HDLParsers:3482 - Could not resolve instantiated unit SDIVIDER_V3_0 in Verilog module work/division_core in any library

ERROR:Simulator:198 - Failed when handling dependencies for module fib_waves

 

fib_waves is the name of waveform file. I get the error when simulating the design with the core made within ProNav.

 

I looked up 3482 and it says that some modules wont simulate with the behavioral model. pipeline divider 3.0 seems to be one such. So I used core gen to make a new pipeline divide core with a structural model  for the purposes of simulation. It does not seem a structural description can be made when using gore gen within ProNav (it only gives behavioral).  When I use the core with the structural model, the simulation does NOT give 3482 and 198....Whats so confusing about this?

 

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Xilinx Employee
Xilinx Employee
10,428 Views
Registered: ‎08-13-2007

Re: How to use Core Generator cores?

This latest information finally explains why you had to generate Structural instead of Behavioral simulation files.

 

You still need to to diff your synthesis report files (e.g. syr) to see what is going on. One can speculate but can't be sure based on the information provided.

You should also make sure that the simulation file only shows up in the behavioral simulation view and not the synthesis/implementation view in ProjNav.

 

bt

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