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Scholar vanmierlo
Registered: ‎06-10-2008

How to use VauxN on XADC



I've found the XADC wizard in the Vivado IPI and added it to my Block Design. The IP block has a VP_VN input that I can make extern. Should I? And if so, what to to with the VHDL std_logic in signals it creates ib the wrappr interface? These lines are not std_logic, now are they? And even I just bring them all the way to the top of my design, am I supposed to constrain them to their already fixed pins? And should I apply an IO_STANDARD? And exactly the same questions about any enabled Vaux pair.


Why is this so badly documented? I know there is an example project in XAPP1182, but that is impossible to open. It requires an ancient Vivado 2013.2 because it has an exported TCL project which all other versions reuse to run. So to save me time on downloading a complete vivado project Xilinx distributes a TCL script which can only be used with a 2GB download of an old Vivado.


Would it really be so hard to just document the steps that I need to take to get this going?



4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎03-21-2008

Re: How to use VauxN on XADC

Hi Maarten,

The vp-vn input is special in that it's connection to the xadc is dedicated. This means you don't have to hook it up in your vhdl code for it to be connected, all you have to do is ensure the xadc converts on this channel.

For any of the other vaux analog inputs, you do have to hook them up in your vhdl code/make external, as this is what tells the sw that you intend on using these package pins.

The std_logic data type should be fine, again it's just used to indicate the are connected to the package inputs. The io standards, etc are documented.

Can you try the xadc wizard - it should include an example design also.

Hope this helps.
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Scholar vanmierlo
Registered: ‎06-10-2008

Re: How to use VauxN on XADC

Hello @jmcgrath,


Thanks for your answer. I was unaware the XADC wizard came with an example. However when I open it, I see no Block Design and no constraints on the analog pins. I'm afraid it doesn't provide me any help.


Is the following how I'm supposed to use the XADC?


With this configuration:


And then I get this generated wrapper:

entity design_1_wrapper is
  port (
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
<snip> FIXED_IO_ps_srstb : inout STD_LOGIC; Vaux0_v_n : in STD_LOGIC; Vaux0_v_p : in STD_LOGIC; Vp_Vn_v_n : in STD_LOGIC; Vp_Vn_v_p : in STD_LOGIC ); end design_1_wrapper;

For which I write these constraints for a Zynq 7010 CLG400:

set_property IOSTANDARD LVCMOS33 [get_ports {Vaux*}]
set_property IOSTANDARD LVCMOS33 [get_ports {Vp*}]

set_property PACKAGE_PIN K9  [get_ports {Vp_Vn_v_p}]
set_property PACKAGE_PIN L10 [get_ports {Vp_Vn_v_n}]
set_property PACKAGE_PIN C20 [get_ports {Vaux0_v_p}]
set_property PACKAGE_PIN B20 [get_ports {Vaux0_v_n}]


I still find this all pretty strange because those signals are not STD_LOGIC and there is no other place where Vp_Vn and Vaux0 pins can be routed. And I also don't understand why they need an IOSTANDARD.


I'm asking because I can't get proper data out of the Vaux channel on Petalinux.



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Xilinx Employee
Xilinx Employee
Registered: ‎03-21-2008

Re: How to use VauxN on XADC

Hi Maarten,


For the pin-constraints:


You are right, vp/vn do not actually need to be hooked up in your vhdl/block-digram - this is because they are dedicated connections. However for consistency, if you DO declare them in your vhdl, then you must treat them like all other analog inputs - and all inputs require pin-constaints. In general it is better to be consistent, rather than create esoteric edge cases.


Also, vaux0 on some devices (ultrascale, ultrascale+) can come from different locations - So specifying the input location is for consistency, and to ensure the design files are forward-compatible for porting designs/ip. 


For the IOSTANDARD constraints:


There is a SW DRC 'protect' the user which specifies that all IO must have pin-constraints, and IO standard constraints. This is to enable other DRCs (which check IO bank rules, etc) to use correct information. In general this gives a higher-quality design. Allowing certain signals to not have these constraints breaks consistency and just opens up edge-cases in how these DRCs would operate.


For the signal data-type:


The reason for the std_logic type - again, you are right that these are of course analog signals, so by definition not std_logic. However, the purpose of these signals are simply to 'declare' them so the hookup of them can be traced through the design hierarchy. This allows the SW to determine if they are hooked up to package pins, etc. A special data-type could have been created for them - but it was seen to offer no benefit over std_logic.


I hope this explains some of the rationale behind why these constraints are required.


I think the bigger question here is why you cannot get proper data out of vaux0.


The 3 main reasons I've seen are:

1) The vaux channel is not being converted - which means it is not in the sequence of channels to convert, or the sequence is not enabled

2) The vaux channel is not hooked up in the design - i.e. the signals do not make it to the top-level, so SW does not enable the HW connectoin for them. This usually ends up with a value ~0.1 to 0.3 volts being measured by the XADC.

3) The positive and negative inputs for a given channel are not used properly. As the inputs are differential - it means both must be conected to the source you are measuring. This often means the 'n' input of the pair is connected to the ground of the source you are measuring and the 'p' side is connected to the signal. The max differential between 'p' and 'n' must also be < 1Volt.


Hope this helps

Registered: ‎06-06-2019

Re: How to use VauxN on XADC

Hey @jmcgrath ..

Thanks for your explanation. I am also trying to use XADC wiz to perform ADC onto my PYNQ - Z1 board. I have included the block design, Verilog codes of my modules and the Jupiter code. 

The issue is perhaps, I am unable to provide analog input to my Vp_Vn: dedicated analog pins for XADC. Due to which the code is stuck in the else part of the if the condition of my Verilog code in which I am doing the conversion. That is, the response of D1 and D2 is not changing with the change of the voltage applied to those pins. or else, there are some other errors.

my adc_register_to_digi module is defined as:

module adc_register_to_digi(digital_in, status, D1, D2, S1, S2);
input [15:0] digital_in; //variable digital_in for storing the digital value of the XADC
input status; //variable for clock signal required for sync.
output D1;
output D2; //output variables to be connected to the digital pins.
output S1;
output S2;
reg D1,D2,S1,S2;

Capture (2).PNG 








Please guide me through this.

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