11-24-2015 02:28 PM
in my design I would like to have 4 FFT engines working in parallel. I connect them to the PS through an AXI-DMA.
If I use up to 2 FFT blocks I can validate the design.
If I add the 3rd FFT block I receive the error
ERROR: [BD 41-237] Bus Interface property ID_WIDTH does not match between /processing_system7_0/S_AXI_ACP(3) and /axi_mem_intercon/m00_couplers/auto_pc/M_AXI(4)
I cannot see what I am doing wrong.
I attach the tcl to regenerate the the block design for the cases with 2 and 3 FFT.
03-09-2016 11:02 PM
See if these help:
03-10-2016 03:36 AM
I don't really know what solved the problem, but I customized the interconnector manually several times with different options and at some point the error vanished