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Scholar beandigital
Scholar
5,217 Views
Registered: ‎04-27-2010

IDELAYCTRL clock

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I am getting the following warning for a Zynq design. I have the IDELAYCTRL clock as a 200 MHz clock that comes from the Zynq clock generator. Is this not the correct thing to do? The design seems to work OK.

Thanks

 

[DRC 23-20] Rule violation (PLIDC-14) IDELAYCTRL REFCLK should be same as ISERDES CLK - The BITSLICE cell IDELAYCTRL system_i/Interface_0/inst/U_idelayctrl REFCLK pin should be driven by the same clock net as the associated ISERDES system_i/Interface_0/inst/U_adc_if/genblk1[0].ISERDESE2_inst CLK or CLKDIV pin.

1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
9,867 Views
Registered: ‎09-20-2012

Re: IDELAYCTRL clock

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Hi @beandigital

 

This message can be ignored if you are using 7 series or Zynq device.

 

This DRC is only applicable to Ultrascale devices.

 

The tool was incorrectly issuing this message for 7 series designs. This is already reported to factory and planned to be fixed in our next release 2016.3.

Thanks,
Deepika.
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2 Replies
Xilinx Employee
Xilinx Employee
9,868 Views
Registered: ‎09-20-2012

Re: IDELAYCTRL clock

Jump to solution

Hi @beandigital

 

This message can be ignored if you are using 7 series or Zynq device.

 

This DRC is only applicable to Ultrascale devices.

 

The tool was incorrectly issuing this message for 7 series designs. This is already reported to factory and planned to be fixed in our next release 2016.3.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Moderator
Moderator
5,210 Views
Registered: ‎01-16-2013

Re: IDELAYCTRL clock

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@beandigital,

 

Check if the following AR#66013 helps.

http://www.xilinx.com/support/answers/66013.html

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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