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Visitor
Visitor
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Registered: ‎05-05-2015

IP Catalog Problem in Vivado 2014.4

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Hi,

 

I'm trying to generate a simple square root IP using CORDIC, and after setting the parameter in the IP customize GUI and hitting OK, I get the following error:

 

ERROR: [Synth 8-4747] shared variables must be of a protected type [c:/IAI/VPR/VHDL/VPR-Z100-SG/VPR.srcs/sources_1/ip/SquareRoot/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd:1399]

 

I'm using Vivado 2014.4. Here is a screenshot of my GUI, any help is appreciated!

 

CORDIC.jpg

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Scholar
Scholar
19,608 Views
Registered: ‎06-05-2013

@anamazi Do remember to set the Language setting to Vhdl 93 before you run the IP in OOC flow.

 

Run below tcl command 

 

set_property vhdl_version vhdl_93 [current_fileset]

 

Then run the IP In OOC flow once done enable 2008 by running tcl command

 

set_property vhdl_version vhdl_2008 [current_fileset]

-Pratham

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Xilinx Employee
Xilinx Employee
10,848 Views
Registered: ‎02-14-2014

Hello @anamazi,

 

I don't think this to be problem with IP customization or generation of output products (from IP perspective) because I am able to generate output products out-of-context successfully for this IP standalone in Vivado 2014.4 with same options specified in the GUI.

 

Have you tried investigating xbip_bram18k_v3_0_vh_rfs.vhd file further as mentioned in the error message? 

Regards,
Ashish
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Visitor
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Registered: ‎05-05-2015
Hi Ashish,

That file is automatically generated by Vivado and is encrypted. How can I look into it?

Thanks,
Ali
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Xilinx Employee
Xilinx Employee
10,827 Views
Registered: ‎02-14-2014

Hello @anamazi,

 

I suspect the problem here is your top level file is having vhdl 2008 constructs (settings enabled) and you are trying to synthesize IP with same settings globally. I think you have followed below AR http://www.xilinx.com/support/answers/62005.html 

I would recommend you to set these IPs OOC and have the OOC synthesis runs not enable vhdl-2008 support. 

Let us know if you still face any problem. 

Regards,
Ashish
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Visitor
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Registered: ‎05-05-2015
Ashish,

Thank you! I guess this must be the reason because I enabled VHDL 2008 a while back to use some "if...else...generate" statements in my code. I'm a beginner in tcl, so I would appreciate if you let me know the steps I need to take to do what you just described.

Thanks,
Ali
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Xilinx Employee
Xilinx Employee
10,793 Views
Registered: ‎02-14-2014

Hello @anamazi,

 

To perform this operation -

 

1. Simply run out-of-context synthesis for IP before enabling vhdl_2008 for the top level module. So it will get synthesized with earlier version of VHDL.

 

2. Then enable vhdl_2008 for the entire design using commands specified in http://www.xilinx.com/support/answers/62005.html

 

Hope this helps.

Regards,
Ashish
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Highlighted
Scholar
Scholar
19,609 Views
Registered: ‎06-05-2013

@anamazi Do remember to set the Language setting to Vhdl 93 before you run the IP in OOC flow.

 

Run below tcl command 

 

set_property vhdl_version vhdl_93 [current_fileset]

 

Then run the IP In OOC flow once done enable 2008 by running tcl command

 

set_property vhdl_version vhdl_2008 [current_fileset]

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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Visitor
Visitor
10,769 Views
Registered: ‎05-05-2015
Thank you guys, problem solved!
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