cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Gangadhara
Contributor
Contributor
199 Views
Registered: ‎11-05-2020

[IP_Flow 19-262] [HDL Parser] Failed to parse top module entity. This can result from an empty entity or module declaration (i.e. no ports or parameters/generics). Check that design unit "fcw_fpga_

i have RTL source file ,i want to make custom ip from source fioles, but when i try to pack the new ip i am getting following error .

  • [IP_Flow 19-262] [HDL Parser] Failed to parse top module entity. This can result from an empty entity or module declaration (i.e. no ports or parameters/generics). Check that design unit "fcw_fpga_top" of HDL file "d:/RD461/FCW_ZCU104_FEB_19/ip_package/src/lib_srl_fifo_v1_0_2/lib_srl_fifo_v1_0_rfs.vhd" is not empty.
  • [IP_Flow 19-258] [HDL Parser] Error parsing HDL file 'd:/RD461/FCW_ZCU104_FEB_19/ip_package/src/lib_srl_fifo_v1_0_2/lib_srl_fifo_v1_0_rfs.vhd'.

Can anyone please provide the solution for it

0 Kudos
1 Reply
mvisser
Observer
Observer
117 Views
Registered: ‎11-06-2018

There is a syntax error in d:/RD461/FCW_ZCU104_FEB_19/ip_package/src/lib_srl_fifo_v1_0_2/lib_srl_fifo_v1_0_rfs.vhd

If you open it up there should be some red squiggles and indications as to what the exact error is.

0 Kudos