[IP_Flow 19-3155] Bus Interface 'video_CLK': ASSOCIATED_RESET port 'video_aresetn' does not exist.
Tragic back story...
I have a video processing block that will be incorporated into a Zynq based design. My video processing block will run at 160 MHz, while the rest of the logic in the design runs at 100 MHz. I wired up my IP and connected the video_aresetn signal to the same peripheral_resetn signal used by all of the 100 MHz logic and got a timing violation. The classic solution to this is to add a reset bridge.
So, I removed the video_aresetn port from my IP block, added 2 flip flops inside the block to create the reset bridge, and went to repackage my IP when I discovered this warning on the "IP Interfaces" tab. Obviously, something inside Vivado knows that AXI Stream interfaces should have both a clock and a reset signal and is helpfully warning me that I forgot the resetn signal for my interface.
This opens up a whole slew of questions for me...
1) How does Vivado know that I need an aresetn signal for this interface? 2) How can I tell it "I know what I'm doing here... I don't need an aresetn signal for this interface." 3) What if I don't know what I'm doing, and I really _do_ need an aresent input for my IP? Why would I need it?
4) Should I have put the 2 flip flops in their own "reset bridge" IP and wired it in at the top level of my block diagram?
5) Does Xilinx already have a reset bridge IP module that I just didn't see?
I'll stop here. Mainly I'm curious to learn how I can make this warning go away. (I hate training myself to ignore warnings!)
Re: [IP_Flow 19-3155] Bus Interface 'video_CLK': ASSOCIATED_RESET port 'video_aresetn' does not exist.
Answering part of my own question (so I can find the answer when I run into this again)... The ASSOCIATED_RESET parameter is associated with the "Bus Parameters" tab for the video clock signal. By deleting that bus parameter, I made the warning go away and told the tool that I know what I'm doing.