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Visitor frederic.ta
Visitor
11,441 Views
Registered: ‎02-16-2015

[IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Version: Vivado 2014.4

 

Hi,

I am working on a project which needs to include a custom IP (IpBus from CACTUS ). I have to generate a new Package IP but I have some understandable errors. I have looked for solutions on the forum but I only found people with same errors and nothing else.

 

I attached a .zip with all .vhd code in this post.

 

How I proceeded to create my Package IP:

Create new project > RTL Project > Target Language: VHDL, Simu Language: VHDL

Add Sources: I added the directory of my .vhd files (custom IP)

Add Existing IP: No > Add Constraints: No

Default Part > I selected my board: Zynq-7 ZC702 > Finish

Tools > Create and Package IP > Package your current project > Finish

 

The packaging was successful but I have errors.

Errors encountered:

custom_param_errors.PNG  

 

[IP_Flow 19-734] Port 'oob_in': Port type name "ipbus_trans_in_array" is not supported

[IP_Flow 19-734] Port 'oob_out': Port type name "ipbus_trans_out_array" is not supported

It seems that it is a compatibility problem with Vivado which doesn’t support custom port definitions, and I should change my design to fix it. There was a topic on this error but it doesn’t solve mine.

Topic: http://forums.xilinx.com/t5/Design-Entry/vivado-ip-packager-and-type-definition-port/td-p/466672

 

The snapshot below is the Ports and Interfaces panel, I annotated the problematic part.

in_out.PNG

I already met [IP_Flow 19-734] once on ports: ipb_in & ipb_out and changed my design to fix it: I switched them to std_logic_vector and changed some connections. But my current problem is that I use a custom type array and I think it is too complex to modify. This is why I ask you for some clues or solutions to solve it.

 

This is the code where custom type array are initialized.

 code_upbus_trans.PNG

 

 

[IP_Flow 19-627] Port 'oob_in': XPath expression failed: Operator "=" found with not enough operands in XPath expression "(others => ('0', b"00000000000000000000000000000000", '0'))".

I think this is related to the previous errors, I founded a topic on it, but I prefer to solve [IP_Flow 19-734] before.

Topic: http://forums.xilinx.com/xlnx/board/crawl_message?board.id=DEENBD&message.id=6767

 

[IP_Flow 19-627] HDL Parameter 'MAC_CFG (Mac Cfg)': XPath expression failed: Undefined parameter "EXTERNAL" found in XPath expression "EXTERNAL".

[IP_Flow 19-627] HDL Parameter 'IP_CFG (Ip Cfg)': XPath expression failed: Undefined parameter "EXTERNAL" found in XPath expression "EXTERNAL".

 

This is my Customization Parameters panel and the error messages:

custom_param.PNG

 

custom_param_errors.PNG

 

Both have the same error tag as above but I have no idea to solve them. It seems that it will be a future release to fix it? (2014.4)?

 

Thanks and Regards,

Frederic

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7 Replies
Moderator
Moderator
11,424 Views
Registered: ‎01-16-2013

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi Frederic,

Please try to synthesis and implement your design before moving for packaging. Please let me know the results of run.
Meanwhile I will try to package your code into IP.

FYI.. 2014.4 is already released long back.

Which version of tool you are using?

Thanks,
Yash
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Visitor frederic.ta
Visitor
11,399 Views
Registered: ‎02-16-2015

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi Yash,

I am under Vivado 2014.4 up from 2013.3 yesterday. I never used Vivado before, I was on ISE 14.7.

I tried to synthesis and implement the design; I thought Vivado did it automatically when I packaged the code. It seemed that I made a lot of mistakes when I tried to fix [IP_Flow 19-734]. So, I used a backup instead (hdl_raw.zip attached) and I think it is better, but other errors appeared.

error_raw_hdl.PNG

Ports ‘oob_in’ and ‘oob_out’ are defined with a custom type, why are they ignored? It think it will be another [IP_Flow 19-734] if I don’t change it.

 

[Synth 8-493] no such design unit 'clock_div' ["C:/Users/taf/Desktop/Zynq_zc702/Projet Vivado 2014.4/project_2/hdl_raw/stretcher.vhd":27]

Is it because ‘clock_div’ in stretcher.vhd is not declared in the main entity (ipbus_ctrl.vhd)? I am currently fixing it, but not completely sure.

I referred to this topic:

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=SYNTHBD&message.id=12204

 

[Synth 8-285] failed synthesizing module 'stretcher' ["C:/Users/taf/Desktop/Zynq_zc702/Projet Vivado 2014.4/project_2/hdl_raw/stretcher.vhd":21]

 [Synth 8-285] failed synthesizing module 'ipbus_ctrl' ["C:/Users/taf/Desktop/Zynq_zc702/Projet Vivado 2014.4/project_2/hdl_raw/ipbus_ctrl.vhd":66]

Because of [Synth 8-493].

 

Normally, if I solve [Synth 8-493], the synthesis and implement should work but I think I still will have [IP_Flow 19-734] when I package it.

 

Thanks and Regards,

Frederic

 

 

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Moderator
Moderator
11,393 Views
Registered: ‎01-16-2013

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi,

Try to fix your code 1st before moving into the IP packaging.

Also If you fixed all errors and pass implementation pass on your files to me.

Thanks,
Yash
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Visitor frederic.ta
Visitor
11,387 Views
Registered: ‎02-16-2015

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi Yash,

 

I fixed my first code and the synthesis pass but I have another problem during the implementation, I use 213 I/O but only 200 are available. There is a topic with the same error but there were unused I/O, for my part it seems all used. Do I have to change the design again or there other solutions?

 

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (213) is greater than number of available sites (200).
The following Groups of I/O terminals have not sufficient capacity

 

Topic: http://forums.xilinx.com/t5/7-Series-FPGAs/Place-30-58-IO-placement-is-infeasible/td-p/503208

imple_error_graph.PNGimple_error_tab.PNG

 

imple_error.PNG

 

 

Thanks,

 

Frederic

Tags (3)
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Xilinx Employee
Xilinx Employee
11,378 Views
Registered: ‎09-20-2012

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi,

 

Is the IP packager issue solved?

 

Please create a new thread for the implementation error.

 

Basically you need to either reduce the number of top level ports in the design or target next bigger device.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor frederic.ta
Visitor
11,366 Views
Registered: ‎02-16-2015

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi,

 

No, I didn't solve the issue with the IP packager and I can't reduce the number of ports. I think I will let my project in stand by and look after another possibility.

Thank for your help,

 

Frederic

0 Kudos
6,109 Views
Registered: ‎06-06-2014

Re: [IP_Flow 19-734] Custom user type errors and [IP_Flow 19-627] error message

Hi,

 

I also like to use custom types for my entities. I found that the tool writes the entry for the port with the right type (my custom type) into the corresponding "component.xml" file despite the error messages. However, when instantiating that IP-Core in another design, the generated wrapper for the top level does have 'std_logic' as type for the custom ports which of course fails durin synthesis.

 

I do not know why the tool assumes std_logic for types it doesn't know instead of just using the unknown type. The tool should really support custom types. In fact, that makes using Vivado and IP-Packager really unproductive. Will this get fixed any time?

Btw. I'm using Vivado-2015.4.

 

Best regards,

Michael

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